Lines Matching +full:4 +full:- +full:ch
8 * SPDX-License-Identifier: Intel
25 300000, /* 4Gb */
88 tck = t_ck[mrc_params->ddr_speed]; /* Clock in picoseconds */ in prog_ddr_timing_control()
89 tcl = mrc_params->params.cl; /* CAS latency in clocks */ in prog_ddr_timing_control()
92 tras = MCEIL(mrc_params->params.ras, tck); in prog_ddr_timing_control()
94 /* Per JEDEC: tWR=15000ps DDR2/3 from 800-1600 */ in prog_ddr_timing_control()
97 twtr = MCEIL(mrc_params->params.wtr, tck); in prog_ddr_timing_control()
98 trrd = MCEIL(mrc_params->params.rrd, tck); in prog_ddr_timing_control()
99 trtp = 4; /* Valid for 800 and 1066, use 5 for 1333 */ in prog_ddr_timing_control()
100 tfaw = MCEIL(mrc_params->params.faw, tck); in prog_ddr_timing_control()
102 wl = 5 + mrc_params->ddr_speed; in prog_ddr_timing_control()
105 dtr0 |= mrc_params->ddr_speed; in prog_ddr_timing_control()
107 tmp1 = tcl - 5; in prog_ddr_timing_control()
108 dtr0 |= ((tcl - 5) << 12); in prog_ddr_timing_control()
110 dtr0 |= ((trp - 5) << 4); /* 5 bit DRAM Clock */ in prog_ddr_timing_control()
112 dtr0 |= ((trcd - 5) << 8); /* 5 bit DRAM Clock */ in prog_ddr_timing_control()
115 tmp2 = wl - 3; in prog_ddr_timing_control()
116 dtr1 |= (wl - 3); in prog_ddr_timing_control()
118 dtr1 |= ((wl + 4 + twr - 14) << 8); /* Change to tWTP */ in prog_ddr_timing_control()
120 dtr1 |= ((MMAX(trtp, 4) - 3) << 28); /* 4 bit DRAM Clock */ in prog_ddr_timing_control()
122 dtr1 |= ((trrd - 4) << 24); /* 4 bit DRAM Clock */ in prog_ddr_timing_control()
124 dtr1 |= (1 << 4); in prog_ddr_timing_control()
126 dtr1 |= ((tras - 14) << 20); /* 6 bit DRAM Clock */ in prog_ddr_timing_control()
128 dtr1 |= ((((tfaw + 1) >> 1) - 5) << 16);/* 4 bit DRAM Clock */ in prog_ddr_timing_control()
129 /* Set 4 Clock CAS to CAS delay (multi-burst) */ in prog_ddr_timing_control()
142 dtr3 |= (2 << 4); in prog_ddr_timing_control()
145 if (mrc_params->ddr_speed == DDRFREQ_800) { in prog_ddr_timing_control()
147 dtr3 |= ((tcl - 5 + 1) << 8); in prog_ddr_timing_control()
148 } else if (mrc_params->ddr_speed == DDRFREQ_1066) { in prog_ddr_timing_control()
150 dtr3 |= ((tcl - 5 + 1) << 8); in prog_ddr_timing_control()
154 dtr3 |= ((4 + wl + twtr - 11) << 13); in prog_ddr_timing_control()
157 if (mrc_params->ddr_speed == DDRFREQ_800) in prog_ddr_timing_control()
158 dtr3 |= ((MMAX(0, 1 - 1)) << 22); in prog_ddr_timing_control()
160 dtr3 |= ((MMAX(0, 2 - 1)) << 22); in prog_ddr_timing_control()
165 dtr4 |= (1 << 4); in prog_ddr_timing_control()
167 dtr4 |= ((1 + tmp1 - tmp2 + 2) << 8); in prog_ddr_timing_control()
169 dtr4 |= ((1 + tmp1 - tmp2 + 2) << 12); in prog_ddr_timing_control()
217 * impact, however simulator complains if enabled non-existing rank. in prog_decode_before_jedec()
220 if (mrc_params->rank_enables & 1) in prog_decode_before_jedec()
222 if (mrc_params->rank_enables & 2) in prog_decode_before_jedec()
248 mrc_params->rd_odt_value == 0 ? DRMC_ODTMODE : 0); in perform_ddr_reset()
261 uint8_t ch; /* channel counter */ in ddrphy_init() local
265 /* For DDR3 --> 0 == 800, 1 == 1066, 2 == 1333 */ in ddrphy_init()
266 uint8_t speed = mrc_params->ddr_speed & 3; in ddrphy_init()
272 cas = mrc_params->params.cl; in ddrphy_init()
273 cwl = 5 + mrc_params->ddr_speed; in ddrphy_init()
285 for (ch = 0; ch < NUM_CHANNELS; ch++) { in ddrphy_init()
286 if (mrc_params->channel_enables & (1 << ch)) { in ddrphy_init()
289 CMDPMCONFIG0 + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
293 CMDCFGREG0 + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
297 CMDPTRREG + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
305 /* Initialize DQ01, DQ23, CMD, CLK-CTL, COMP modules */ in ddrphy_init()
309 for (ch = 0; ch < NUM_CHANNELS; ch++) { in ddrphy_init()
310 if (mrc_params->channel_enables & (1 << ch)) { in ddrphy_init()
311 /* DQ01-DQ23 */ in ddrphy_init()
315 /* Analog MUX select - IO2xCLKSEL */ in ddrphy_init()
319 ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
323 switch (mrc_params->rd_odt_value) { in ddrphy_init()
342 ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
348 ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
356 temp -= 0x01010101; in ddrphy_init()
359 temp -= 0x02020202; in ddrphy_init()
362 temp -= 0x03030303; in ddrphy_init()
365 temp -= 0x04040404; in ddrphy_init()
373 ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
395 ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
401 ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
404 switch (mrc_params->rd_odt_value) { in ddrphy_init()
419 ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
425 ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
434 ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
435 ((cas + 7) << 16) | ((cas - 4) << 8) | in ddrphy_init()
436 ((cwl - 2) << 0), 0x003f1f1f); in ddrphy_init()
440 ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
441 ((cas + 7) << 16) | ((cas - 4) << 8) | in ddrphy_init()
442 ((cwl - 2) << 0), 0x003f1f1f); in ddrphy_init()
448 ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
453 ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
460 ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
465 ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
473 ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
480 ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
483 /* Per-Bit De-Skew Enable */ in ddrphy_init()
487 ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
489 /* Per-Bit De-Skew Enable */ in ddrphy_init()
493 ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
499 CMDOBSCKEBBCTL + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
504 CMDCFGREG0 + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
509 CMDRCOMPODT + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
516 CMDPMDLYREG4 + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
524 CMDPMDLYREG3 + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
528 CMDPMDLYREG2 + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
532 CMDPMDLYREG1 + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
536 CMDPMDLYREG0 + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
540 CMDPMCONFIG0 + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
545 CMDMDLLCTL + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
546 (0x3 << 4) | (0x7 << 0), 0x7f); in ddrphy_init()
548 /* CLK-CTL */ in ddrphy_init()
550 CCOBSCKEBBCTL + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
554 CCCFGREG0 + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
558 CCRCOMPODT + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
562 CCMDLLCTL + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
563 (0x3 << 4) | (0x7 << 0), 0x7f); in ddrphy_init()
567 * - DQ/DQS/DM RON: 32 Ohm in ddrphy_init()
568 * - CTRL/CMD RON: 27 Ohm in ddrphy_init()
569 * - CLK RON: 26 Ohm in ddrphy_init()
573 DQVREFCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
577 CMDVREFCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
581 CLKVREFCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
585 DQSVREFCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
589 CTLVREFCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
594 COMPEN1CH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
600 DQVREFCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
604 DQSVREFCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
608 CLKVREFCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
614 * - DQ/DQS/DM/CLK SR: 4V/ns, in ddrphy_init()
615 * - CTRL/CMD SR: 1.5V/ns in ddrphy_init()
618 (0x0b << 4) | (0x0b << 0); in ddrphy_init()
621 DLYSELCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
625 TCOVREFCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
630 CCBUFODTCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
635 COMPEN0CH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
642 DQDRVPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
647 DQDRVPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
652 DQDLYPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
657 DQDLYPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
662 DQODTPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
667 DQODTPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
672 DQTCOPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
676 DQTCOPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
682 DQSDRVPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
687 DQSDRVPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
692 DQSDLYPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
697 DQSDLYPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
702 DQSODTPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
707 DQSODTPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
712 DQSTCOPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
716 DQSTCOPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
722 CLKDRVPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
727 CLKDRVPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
732 CLKDLYPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
737 CLKDLYPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
742 CLKODTPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
747 CLKODTPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
752 CLKTCOPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
756 CLKTCOPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
762 CMDDRVPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
767 CMDDRVPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
772 CMDDLYPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
777 CMDDLYPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
784 CTLDRVPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
789 CTLDRVPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
794 CTLDLYPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
799 CTLDLYPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
806 DQTCOPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
811 DQTCOPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
818 DQSTCOPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
823 DQSTCOPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
830 CLKTCOPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
835 CLKTCOPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
842 set_wcmd(ch, ddr_wcmd[PLATFORM_ID]); in ddrphy_init()
844 set_wcmd(ch, ddr_wclk[PLATFORM_ID] + HALF_CLK); in ddrphy_init()
848 if (mrc_params->rank_enables & (1 << rk)) { in ddrphy_init()
849 set_wclk(ch, rk, ddr_wclk[PLATFORM_ID]); in ddrphy_init()
851 set_wctl(ch, rk, ddr_wctl[PLATFORM_ID]); in ddrphy_init()
853 set_wctl(ch, rk, ddr_wclk[PLATFORM_ID] + HALF_CLK); in ddrphy_init()
940 for (ch = 0; ch < NUM_CHANNELS; ch++) { in ddrphy_init()
941 if (mrc_params->channel_enables & (1 << ch)) { in ddrphy_init()
942 /* DQ01-DQ23 */ in ddrphy_init()
949 ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
961 CMDMDLLCTL + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
964 /* CLK-CTL */ in ddrphy_init()
966 CCMDLLCTL + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
976 for (ch = 0; ch < NUM_CHANNELS; ch++) { in ddrphy_init()
977 if (mrc_params->channel_enables & (1 << ch)) { in ddrphy_init()
978 /* DQ01-DQ23 */ in ddrphy_init()
985 ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
997 CMDMDLLCTL + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
1000 /* CLK-CTL */ in ddrphy_init()
1002 CCMDLLCTL + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
1012 for (ch = 0; ch < NUM_CHANNELS; ch++) { in ddrphy_init()
1013 if (mrc_params->channel_enables & (1 << ch)) { in ddrphy_init()
1014 /* DQ01-DQ23 */ in ddrphy_init()
1020 (mrc_params->channel_width == X16)) ? in ddrphy_init()
1029 ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
1036 ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
1043 ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
1055 CMDDLLTXCTL + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
1064 for (ch = 0; ch < NUM_CHANNELS; ch++) { in ddrphy_init()
1065 if (mrc_params->channel_enables & (1 << ch)) { in ddrphy_init()
1074 ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
1080 ECCCLKALIGNREG2 + ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
1083 CMDCLKALIGNREG2 + ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
1086 CCCLKALIGNREG2 + ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
1089 CMDCLKALIGNREG0 + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
1096 CMDCLKALIGNREG1 + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
1102 CMDCLKALIGNREG2 + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
1103 (0x10 << 16) | (0x4 << 8) | (0x2 << 4), in ddrphy_init()
1108 CMDCLKALIGNREG0 + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
1111 CMDCLKALIGNREG0 + ch * DDRIOCCC_CH_OFFSET) & in ddrphy_init()
1118 CMDPTRREG + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
1124 COMPEN0CH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
1133 COMPEN0CH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
1140 CMDCFGREG0 + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
1145 CMDPMCONFIG0 + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
1198 if ((mrc_params->rank_enables & (1 << rank)) == 0) in perform_jedec_init()
1205 (mrc_params->rd_odt_value == 0 ? DRMC_ODTMODE : 0)); in perform_jedec_init()
1209 * BIT[15:11] --> Always "0" in perform_jedec_init()
1210 * BIT[10:09] --> Rtt_WR: want "Dynamic ODT Off" (0) in perform_jedec_init()
1211 * BIT[08] --> Always "0" in perform_jedec_init()
1212 * BIT[07] --> SRT: use sr_temp_range in perform_jedec_init()
1213 * BIT[06] --> ASR: want "Manual SR Reference" (0) in perform_jedec_init()
1214 * BIT[05:03] --> CWL: use oem_tCWL in perform_jedec_init()
1215 * BIT[02:00] --> PASR: want "Full Array" (0) in perform_jedec_init()
1218 wl = 5 + mrc_params->ddr_speed; in perform_jedec_init()
1219 emrs2_cmd |= ((wl - 5) << 9); in perform_jedec_init()
1220 emrs2_cmd |= (mrc_params->sr_temp_range << 13); in perform_jedec_init()
1224 * BIT[15:03] --> Always "0" in perform_jedec_init()
1225 * BIT[02] --> MPR: want "Normal Operation" (0) in perform_jedec_init()
1226 * BIT[01:00] --> MPR_Loc: want "Predefined Pattern" (0) in perform_jedec_init()
1232 * BIT[15:13] --> Always "0" in perform_jedec_init()
1233 * BIT[12:12] --> Qoff: want "Output Buffer Enabled" (0) in perform_jedec_init()
1234 * BIT[11:11] --> TDQS: want "Disabled" (0) in perform_jedec_init()
1235 * BIT[10:10] --> Always "0" in perform_jedec_init()
1236 * BIT[09,06,02] --> Rtt_nom: use rtt_nom_value in perform_jedec_init()
1237 * BIT[08] --> Always "0" in perform_jedec_init()
1238 * BIT[07] --> WR_LVL: want "Disabled" (0) in perform_jedec_init()
1239 * BIT[05,01] --> DIC: use ron_value in perform_jedec_init()
1240 * BIT[04:03] --> AL: additive latency want "0" (0) in perform_jedec_init()
1241 * BIT[00] --> DLL: want "Enable" (0) in perform_jedec_init()
1244 * 00 --> RZQ/6 (40ohm) in perform_jedec_init()
1245 * 01 --> RZQ/7 (34ohm) in perform_jedec_init()
1246 * 1* --> RESERVED in perform_jedec_init()
1249 * 000 --> Disabled in perform_jedec_init()
1250 * 001 --> RZQ/4 ( 60ohm) in perform_jedec_init()
1251 * 010 --> RZQ/2 (120ohm) in perform_jedec_init()
1252 * 011 --> RZQ/6 ( 40ohm) in perform_jedec_init()
1253 * 1** --> RESERVED in perform_jedec_init()
1258 if (mrc_params->ron_value == 0) in perform_jedec_init()
1263 if (mrc_params->rtt_nom_value == 0) in perform_jedec_init()
1265 else if (mrc_params->rtt_nom_value == 1) in perform_jedec_init()
1267 else if (mrc_params->rtt_nom_value == 2) in perform_jedec_init()
1271 mrc_params->mrs1 = emrs1_cmd >> 6; in perform_jedec_init()
1275 * BIT[15:13] --> Always "0" in perform_jedec_init()
1276 * BIT[12] --> PPD: for Quark (1) in perform_jedec_init()
1277 * BIT[11:09] --> WR: use oem_tWR in perform_jedec_init()
1278 * BIT[08] --> DLL: want "Reset" (1, self clearing) in perform_jedec_init()
1279 * BIT[07] --> MODE: want "Normal" (0) in perform_jedec_init()
1280 * BIT[06:04,02] --> CL: use oem_tCAS in perform_jedec_init()
1281 * BIT[03] --> RD_BURST_TYPE: want "Interleave" (1) in perform_jedec_init()
1282 * BIT[01:00] --> BL: want "8 Fixed" (0) in perform_jedec_init()
1284 * 0 --> 16 in perform_jedec_init()
1285 * 1 --> 5 in perform_jedec_init()
1286 * 2 --> 6 in perform_jedec_init()
1287 * 3 --> 7 in perform_jedec_init()
1288 * 4 --> 8 in perform_jedec_init()
1289 * 5 --> 10 in perform_jedec_init()
1290 * 6 --> 12 in perform_jedec_init()
1291 * 7 --> 14 in perform_jedec_init()
1294 * BIT[06:04] use oem_tCAS-4 in perform_jedec_init()
1300 tck = t_ck[mrc_params->ddr_speed]; in perform_jedec_init()
1301 /* Per JEDEC: tWR=15000ps DDR2/3 from 800-1600 */ in perform_jedec_init()
1303 mrs0_cmd |= ((twr - 4) << 15); in perform_jedec_init()
1307 if ((mrc_params->rank_enables & (1 << rank)) == 0) in perform_jedec_init()
1359 uint8_t ch, rk, bl; in restore_timings() local
1360 const struct mrc_timings *mt = &mrc_params->timings; in restore_timings()
1362 for (ch = 0; ch < NUM_CHANNELS; ch++) { in restore_timings()
1365 set_rcvn(ch, rk, bl, mt->rcvn[ch][rk][bl]); in restore_timings()
1366 set_rdqs(ch, rk, bl, mt->rdqs[ch][rk][bl]); in restore_timings()
1367 set_wdqs(ch, rk, bl, mt->wdqs[ch][rk][bl]); in restore_timings()
1368 set_wdq(ch, rk, bl, mt->wdq[ch][rk][bl]); in restore_timings()
1371 set_vref(ch, bl, mt->vref[ch][bl]); in restore_timings()
1374 set_wctl(ch, rk, mt->wctl[ch][rk]); in restore_timings()
1376 set_wcmd(ch, mt->wcmd[ch]); in restore_timings()
1388 uint8_t ch, rk, bl; in default_timings() local
1390 for (ch = 0; ch < NUM_CHANNELS; ch++) { in default_timings()
1393 set_rdqs(ch, rk, bl, 24); in default_timings()
1396 set_vref(ch, bl, 32); in default_timings()
1410 uint8_t ch; /* channel counter */ in rcvn_cal() local
1413 uint8_t bl_divisor = (mrc_params->channel_width == X16) ? 2 : 1; in rcvn_cal()
1451 for (ch = 0; ch < NUM_CHANNELS; ch++) { in rcvn_cal()
1452 if (mrc_params->channel_enables & (1 << ch)) { in rcvn_cal()
1455 if (mrc_params->rank_enables & (1 << rk)) { in rcvn_cal()
1460 mrc_post_code(0x05, 0x10 + ((ch << 4) | rk)); in rcvn_cal()
1463 /* et hard-coded timing values */ in rcvn_cal()
1465 set_rcvn(ch, rk, bl, ddr_rcvn[PLATFORM_ID]); in rcvn_cal()
1472 ch * DDRIODQ_CH_OFFSET, in rcvn_cal()
1477 /* 1x CLK domain timing is cas-4 */ in rcvn_cal()
1478 delay[bl] = (4 + 1) * FULL_CLK; in rcvn_cal()
1480 set_rcvn(ch, rk, bl, delay[bl]); in rcvn_cal()
1484 find_rising_edge(mrc_params, delay, ch, rk, true); in rcvn_cal()
1486 /* Now increase delay by 32 PI (1/4 CLK) to place in center of high pulse */ in rcvn_cal()
1489 set_rcvn(ch, rk, bl, delay[bl]); in rcvn_cal()
1493 temp = sample_dqs(mrc_params, ch, rk, true); in rcvn_cal()
1497 delay[bl] -= FULL_CLK; in rcvn_cal()
1498 set_rcvn(ch, rk, bl, delay[bl]); in rcvn_cal()
1501 training_message(ch, rk, bl); in rcvn_cal()
1511 /* Finally increment delay by 32 PI (1/4 CLK) to place in center of preamble */ in rcvn_cal()
1515 final_delay[ch][bl] += delay[bl]; in rcvn_cal()
1517 set_rcvn(ch, rk, bl, final_delay[ch][bl] / num_ranks_enabled); in rcvn_cal()
1520 /* Finally increment delay by 32 PI (1/4 CLK) to place in center of preamble */ in rcvn_cal()
1523 set_rcvn(ch, rk, bl, delay[bl]); in rcvn_cal()
1532 ch * DDRIODQ_CH_OFFSET, in rcvn_cal()
1557 uint8_t ch; /* channel counter */ in wr_level() local
1560 uint8_t bl_divisor = (mrc_params->channel_width == X16) ? 2 : 1; in wr_level()
1579 * where non-static copies the data onto the stack every time this in wr_level()
1597 for (ch = 0; ch < NUM_CHANNELS; ch++) { in wr_level()
1598 if (mrc_params->channel_enables & (1 << ch)) { in wr_level()
1601 if (mrc_params->rank_enables & (1 << rk)) { in wr_level()
1606 mrc_post_code(0x06, 0x10 + ((ch << 4) | rk)); in wr_level()
1610 set_wdqs(ch, rk, bl, ddr_wdqs[PLATFORM_ID]); in wr_level()
1611 set_wdq(ch, rk, bl, ddr_wdqs[PLATFORM_ID] - QRTR_CLK); in wr_level()
1638 * Enable Sandy Bridge Mode (WDQ Tri-State) & in wr_level()
1642 DQCTL + DDRIODQ_BL_OFFSET * bl + DDRIODQ_CH_OFFSET * ch, in wr_level()
1649 CCDDR3RESETCTL + DDRIOCCC_CH_OFFSET * ch, in wr_level()
1655 * CLK0 --> RK0 in wr_level()
1656 * CLK1 --> RK1 in wr_level()
1658 delay[bl] = get_wclk(ch, rk); in wr_level()
1660 set_wdqs(ch, rk, bl, delay[bl]); in wr_level()
1664 find_rising_edge(mrc_params, delay, ch, rk, false); in wr_level()
1668 CCDDR3RESETCTL + DDRIOCCC_CH_OFFSET * ch, in wr_level()
1672 /* Disable Sandy Bridge Mode & Ensure 4 WDQS pulses during normal operation */ in wr_level()
1674 DQCTL + DDRIODQ_BL_OFFSET * bl + DDRIODQ_CH_OFFSET * ch, in wr_level()
1686 dram_init_command(DCMD_MRS1(rk, mrc_params->mrs1)); in wr_level()
1694 mrc_post_code(0x06, 0x30 + ((ch << 4) | rk)); in wr_level()
1702 mrc_params->hte_setup = 1; in wr_level()
1706 delay[bl] = get_wdqs(ch, rk, bl) + FULL_CLK; in wr_level()
1707 set_wdqs(ch, rk, bl, delay[bl]); in wr_level()
1710 * (WDQ = WDQS - 32 PI) in wr_level()
1712 set_wdq(ch, rk, bl, (delay[bl] - QRTR_CLK)); in wr_level()
1716 address = get_addr(ch, rk); in wr_level()
1723 mrc_params->hte_setup = 1; in wr_level()
1730 delay[bl] -= FULL_CLK; in wr_level()
1731 set_wdqs(ch, rk, bl, delay[bl]); in wr_level()
1732 /* program WDQ timings based on WDQS (WDQ = WDQS - 32 PI) */ in wr_level()
1733 set_wdq(ch, rk, bl, delay[bl] - QRTR_CLK); in wr_level()
1743 final_delay[ch][bl] += delay[bl]; in wr_level()
1744 set_wdqs(ch, rk, bl, final_delay[ch][bl] / num_ranks_enabled); in wr_level()
1745 /* program WDQ timings based on WDQS (WDQ = WDQS - 32 PI) */ in wr_level()
1746 set_wdq(ch, rk, bl, final_delay[ch][bl] / num_ranks_enabled - QRTR_CLK); in wr_level()
1766 dpmc0 |= (4 << 16); in prog_page_ctrl()
1787 * NOTE: this algorithm assumes the eye curves have a one-to-one relationship,
1788 * meaning for each X the curve has only one Y and vice-a-versa.
1792 uint8_t ch; /* channel counter */ in rd_train() local
1795 uint8_t bl_divisor = (mrc_params->channel_width == X16) ? 2 : 1; in rd_train()
1825 for (ch = 0; ch < NUM_CHANNELS; ch++) { in rd_train()
1826 if (mrc_params->channel_enables & (1 << ch)) { in rd_train()
1828 if (mrc_params->rank_enables & (1 << rk)) { in rd_train()
1832 set_rdqs(ch, rk, bl, ddr_rdqs[PLATFORM_ID]); in rd_train()
1840 for (ch = 0; ch < NUM_CHANNELS; ch++) { in rd_train()
1841 if (mrc_params->channel_enables & (1 << ch)) { in rd_train()
1843 if (mrc_params->rank_enables & (1 << rk)) { in rd_train()
1848 x_coordinate[L][B][ch][rk][bl] = RDQS_MIN; in rd_train()
1849 x_coordinate[R][B][ch][rk][bl] = RDQS_MAX; in rd_train()
1850 x_coordinate[L][T][ch][rk][bl] = RDQS_MIN; in rd_train()
1851 x_coordinate[R][T][ch][rk][bl] = RDQS_MAX; in rd_train()
1853 y_coordinate[L][B][ch][bl] = VREF_MIN; in rd_train()
1854 y_coordinate[R][B][ch][bl] = VREF_MIN; in rd_train()
1855 y_coordinate[L][T][ch][bl] = VREF_MAX; in rd_train()
1856 y_coordinate[R][T][ch][bl] = VREF_MAX; in rd_train()
1878 for (ch = 0; ch < NUM_CHANNELS; ch++) { in rd_train()
1879 if (mrc_params->channel_enables & (0x1 << ch)) { in rd_train()
1881 if (mrc_params->rank_enables & in rd_train()
1887 set_rdqs(ch, rk, bl, in rd_train()
1888 x_coordinate[side_x][side_y][ch][rk][bl]); in rd_train()
1889 set_vref(ch, bl, in rd_train()
1890 y_coordinate[side_x][side_y][ch][bl]); in rd_train()
1894 address = get_addr(ch, rk); in rd_train()
1897 mrc_params->hte_setup = 1; in rd_train()
1912 x_coordinate[L][side_y][ch][rk][bl] += RDQS_STEP; in rd_train()
1914 x_coordinate[R][side_y][ch][rk][bl] -= RDQS_STEP; in rd_train()
1917 if ((x_coordinate[L][side_y][ch][rk][bl] > (RDQS_MAX - MIN_RDQS_EYE)) || in rd_train()
1918 (x_coordinate[R][side_y][ch][rk][bl] < (RDQS_MIN + MIN_RDQS_EYE)) || in rd_train()
1919 (x_coordinate[L][side_y][ch][rk][bl] == in rd_train()
1920 x_coordinate[R][side_y][ch][rk][bl])) { in rd_train()
1926 y_coordinate[side_x][B][ch][bl] += VREF_STEP; in rd_train()
1928 y_coordinate[side_x][T][ch][bl] -= VREF_STEP; in rd_train()
1931 if ((y_coordinate[side_x][B][ch][bl] > (VREF_MAX - MIN_VREF_EYE)) || in rd_train()
1932 (y_coordinate[side_x][T][ch][bl] < (VREF_MIN + MIN_VREF_EYE)) || in rd_train()
1933 (y_coordinate[side_x][B][ch][bl] == y_coordinate[side_x][T][ch][bl])) { in rd_train()
1935 training_message(ch, rk, bl); in rd_train()
1939 set_vref(ch, bl, y_coordinate[side_x][side_y][ch][bl]); in rd_train()
1941 x_coordinate[side_x][side_y][ch][rk][bl] = in rd_train()
1947 set_rdqs(ch, rk, bl, x_coordinate[side_x][side_y][ch][rk][bl]); in rd_train()
1962 for (ch = 0; ch < NUM_CHANNELS; ch++) { in rd_train()
1963 if (mrc_params->channel_enables & (1 << ch)) { in rd_train()
1965 if (mrc_params->rank_enables & (1 << rk)) { in rd_train()
1972 "RDQS T/B eye rank%d lane%d : %d-%d %d-%d\n", in rd_train()
1974 x_coordinate[L][T][ch][rk][bl], in rd_train()
1975 x_coordinate[R][T][ch][rk][bl], in rd_train()
1976 x_coordinate[L][B][ch][rk][bl], in rd_train()
1977 x_coordinate[R][B][ch][rk][bl]); in rd_train()
1980 temp1 = (x_coordinate[R][T][ch][rk][bl] + x_coordinate[L][T][ch][rk][bl]) / 2; in rd_train()
1982 temp2 = (x_coordinate[R][B][ch][rk][bl] + x_coordinate[L][B][ch][rk][bl]) / 2; in rd_train()
1984 x_center[ch][rk][bl] = (uint8_t) ((temp1 + temp2) / 2); in rd_train()
1988 "VREF R/L eye lane%d : %d-%d %d-%d\n", in rd_train()
1990 y_coordinate[R][B][ch][bl], in rd_train()
1991 y_coordinate[R][T][ch][bl], in rd_train()
1992 y_coordinate[L][B][ch][bl], in rd_train()
1993 y_coordinate[L][T][ch][bl]); in rd_train()
1996 temp1 = (y_coordinate[R][T][ch][bl] + y_coordinate[R][B][ch][bl]) / 2; in rd_train()
1998 temp2 = (y_coordinate[L][T][ch][bl] + y_coordinate[L][B][ch][bl]) / 2; in rd_train()
2000 y_center[ch][bl] = (uint8_t) ((temp1 + temp2) / 2); in rd_train()
2014 for (ch = 0; ch < NUM_CHANNELS; ch++) { in rd_train()
2015 if (mrc_params->channel_enables & (1 << ch)) { in rd_train()
2017 if (mrc_params->rank_enables & (1 << rk)) { in rd_train()
2020 set_rdqs(ch, rk, bl, x_center[ch][rk][bl] - (MIN_RDQS_EYE / 2)); in rd_train()
2022 set_rdqs(ch, rk, bl, x_center[ch][rk][bl] + (MIN_RDQS_EYE / 2)); in rd_train()
2025 set_vref(ch, bl, y_center[ch][bl] - (MIN_VREF_EYE / 2)); in rd_train()
2027 set_vref(ch, bl, y_center[ch][bl] + (MIN_VREF_EYE / 2)); in rd_train()
2035 mrc_params->hte_setup = 1; in rd_train()
2049 for (ch = 0; ch < NUM_CHANNELS; ch++) { in rd_train()
2050 if (mrc_params->channel_enables & (1 << ch)) { in rd_train()
2052 if (mrc_params->rank_enables & (1 << rk)) { in rd_train()
2060 final_delay[ch][bl] += x_center[ch][rk][bl]; in rd_train()
2061 set_rdqs(ch, rk, bl, final_delay[ch][bl] / num_ranks_enabled); in rd_train()
2063 set_rdqs(ch, rk, bl, x_center[ch][rk][bl]); in rd_train()
2066 set_vref(ch, bl, y_center[ch][bl]); in rd_train()
2083 * in WR_LVL) +/- 32 PIs (+/- 1/4 CLK) and collapse the eye until all data
2090 uint8_t ch; /* channel counter */ in wr_train() local
2093 uint8_t bl_divisor = (mrc_params->channel_width == X16) ? 2 : 1; in wr_train()
2117 for (ch = 0; ch < NUM_CHANNELS; ch++) { in wr_train()
2118 if (mrc_params->channel_enables & (1 << ch)) { in wr_train()
2120 if (mrc_params->rank_enables & (1 << rk)) { in wr_train()
2124 set_wdq(ch, rk, bl, ddr_wdq[PLATFORM_ID]); in wr_train()
2132 for (ch = 0; ch < NUM_CHANNELS; ch++) { in wr_train()
2133 if (mrc_params->channel_enables & (1 << ch)) { in wr_train()
2135 if (mrc_params->rank_enables & (1 << rk)) { in wr_train()
2141 * WDQ = (WDQS - QRTR_CLK) in wr_train()
2142 * +/- QRTR_CLK in wr_train()
2144 temp = get_wdqs(ch, rk, bl) - QRTR_CLK; in wr_train()
2145 delay[L][ch][rk][bl] = temp - QRTR_CLK; in wr_train()
2146 delay[R][ch][rk][bl] = temp + QRTR_CLK; in wr_train()
2170 for (ch = 0; ch < NUM_CHANNELS; ch++) { in wr_train()
2171 if (mrc_params->channel_enables & (1 << ch)) { in wr_train()
2173 if (mrc_params->rank_enables & in wr_train()
2178 set_wdq(ch, rk, bl, delay[side][ch][rk][bl]); in wr_train()
2186 for (ch = 0; ch < NUM_CHANNELS; ch++) { in wr_train()
2187 if (mrc_params->channel_enables & (1 << ch)) { in wr_train()
2189 if (mrc_params->rank_enables & in wr_train()
2192 address = get_addr(ch, rk); in wr_train()
2195 mrc_params->hte_setup = 1; in wr_train()
2208 delay[L][ch][rk][bl] += WDQ_STEP; in wr_train()
2210 delay[R][ch][rk][bl] -= WDQ_STEP; in wr_train()
2213 if (delay[L][ch][rk][bl] != delay[R][ch][rk][bl]) { in wr_train()
2218 set_wdq(ch, rk, bl, in wr_train()
2219 delay[side][ch][rk][bl]); in wr_train()
2225 training_message(ch, rk, bl); in wr_train()
2240 for (ch = 0; ch < NUM_CHANNELS; ch++) { in wr_train()
2241 if (mrc_params->channel_enables & (1 << ch)) { in wr_train()
2243 if (mrc_params->rank_enables & (1 << rk)) { in wr_train()
2250 "WDQ eye rank%d lane%d : %d-%d\n", in wr_train()
2252 delay[L][ch][rk][bl], in wr_train()
2253 delay[R][ch][rk][bl]); in wr_train()
2255 temp = (delay[R][ch][rk][bl] + delay[L][ch][rk][bl]) / 2; in wr_train()
2258 final_delay[ch][bl] += temp; in wr_train()
2259 set_wdq(ch, rk, bl, in wr_train()
2260 final_delay[ch][bl] / num_ranks_enabled); in wr_train()
2262 set_wdq(ch, rk, bl, temp); in wr_train()
2282 uint8_t ch, rk, bl; in store_timings() local
2283 struct mrc_timings *mt = &mrc_params->timings; in store_timings()
2285 for (ch = 0; ch < NUM_CHANNELS; ch++) { in store_timings()
2288 mt->rcvn[ch][rk][bl] = get_rcvn(ch, rk, bl); in store_timings()
2289 mt->rdqs[ch][rk][bl] = get_rdqs(ch, rk, bl); in store_timings()
2290 mt->wdqs[ch][rk][bl] = get_wdqs(ch, rk, bl); in store_timings()
2291 mt->wdq[ch][rk][bl] = get_wdq(ch, rk, bl); in store_timings()
2294 mt->vref[ch][bl] = get_vref(ch, bl); in store_timings()
2297 mt->wctl[ch][rk] = get_wctl(ch, rk); in store_timings()
2300 mt->wcmd[ch] = get_wcmd(ch); in store_timings()
2304 mt->ddr_speed = mrc_params->ddr_speed; in store_timings()
2316 if (mrc_params->scrambling_enables == 0) in enable_scrambling()
2322 lfsr = mrc_params->timings.scrambler_seed; in enable_scrambling()
2324 if (mrc_params->boot_mode == BM_COLD) { in enable_scrambling()
2347 mrc_params->timings.scrambler_seed = lfsr; in enable_scrambling()
2380 dpmc0 |= (mrc_params->power_down_disable << 25); in prog_ddr_control()
2383 dpmc0 |= (4 << 16); in prog_ddr_control()
2387 /* CMDTRIST = 2h - CMD/ADDR are tristated when no valid command */ in prog_ddr_control()
2401 u8 density = mrc_params->params.density; in prog_dra_drb()
2410 if (mrc_params->rank_enables & 1) in prog_dra_drb()
2412 if (mrc_params->rank_enables & 2) in prog_dra_drb()
2414 if (mrc_params->dram_width == X16) { in prog_dra_drb()
2415 drp |= (1 << 4); in prog_dra_drb()
2420 * Density encoding in struct dram_params: 0=512Mb, 1=Gb, 2=2Gb, 3=4Gb in prog_dra_drb()
2424 density = 4; in prog_dra_drb()
2426 drp |= ((density - 1) << 6); in prog_dra_drb()
2427 drp |= ((density - 1) << 11); in prog_dra_drb()
2430 drp |= (mrc_params->address_mode << 14); in prog_dra_drb()
2465 drfc |= (mrc_params->refresh_rate << 12); in change_refresh_period()
2482 * Configure DDRPHY for Auto-Refresh, Periodic Compensations,
2483 * Dynamic Diff-Amp, ZQSPERIOD, Auto-Precharge, CKE Power-Down
2496 * Enable Auto-Refresh, Periodic Compensations, Dynamic Diff-Amp, in set_auto_refresh()
2497 * ZQSPERIOD, Auto-Precharge, CKE Power-Down in set_auto_refresh()
2500 if (mrc_params->channel_enables & (1 << channel)) { in set_auto_refresh()
2505 switch (mrc_params->rd_odt_value) { in set_auto_refresh()
2532 if (mrc_params->rank_enables & (1 << rank)) in set_auto_refresh()
2555 if (mrc_params->ecc_enables == 0) in ecc_enable()
2577 mrc_params->mem_size -= mrc_params->mem_size / 8; in ecc_enable()
2580 if (mrc_params->boot_mode != BM_S3) { in ecc_enable()
2591 * if error detected it is indicated in mrc_params->status
2604 mrc_params->status = ((result == 0) ? MRC_SUCCESS : MRC_E_MEMTEST); in memory_test()