35 	msr_t msr;  in enable_vmx()  local
42 	msr = msr_read(MSR_IA32_FEATURE_CONTROL);  in enable_vmx()
44 	if (msr.lo & (1 << 0)) {  in enable_vmx()
55 	msr.hi = 0;  in enable_vmx()
56 	msr.lo = 0;  in enable_vmx()
77 		msr.lo |= (1 << 2);  in enable_vmx()
79 			msr.lo |= (1 << 1);  in enable_vmx()
82 	msr_write(MSR_IA32_FEATURE_CONTROL, msr);  in enable_vmx()
164 	msr_t msr = msr_read(MSR_PLATFORM_INFO);  in set_power_limits()  local
173 	if (!(msr.lo & PLATFORM_INFO_SET_TDP))  in set_power_limits()
177 	msr = msr_read(MSR_PKG_POWER_SKU_UNIT);  in set_power_limits()
178 	power_unit = 2 << ((msr.lo & 0xf) - 1);  in set_power_limits()
181 	msr = msr_read(MSR_PKG_POWER_SKU);  in set_power_limits()
182 	tdp = msr.lo & 0x7fff;  in set_power_limits()
183 	min_power = (msr.lo >> 16) & 0x7fff;  in set_power_limits()
184 	max_power = msr.hi & 0x7fff;  in set_power_limits()
185 	max_time = (msr.hi >> 16) & 0x7f;  in set_power_limits()
217 		msr = msr_read(MSR_CONFIG_TDP_NOMINAL);  in set_power_limits()
219 		limit.lo = msr.lo & 0xff;  in set_power_limits()
227 	msr_t msr;  in configure_c_states()  local
229 	msr = msr_read(MSR_PMG_CST_CONFIG_CTL);  in configure_c_states()
230 	msr.lo |= (1 << 28);	/* C1 Auto Undemotion Enable */  in configure_c_states()
231 	msr.lo |= (1 << 27);	/* C3 Auto Undemotion Enable */  in configure_c_states()
232 	msr.lo |= (1 << 26);	/* C1 Auto Demotion Enable */  in configure_c_states()
233 	msr.lo |= (1 << 25);	/* C3 Auto Demotion Enable */  in configure_c_states()
234 	msr.lo &= ~(1 << 10);	/* Disable IO MWAIT redirection */  in configure_c_states()
235 	msr.lo |= 7;		/* No package C-state limit */  in configure_c_states()
236 	msr_write(MSR_PMG_CST_CONFIG_CTL, msr);  in configure_c_states()
238 	msr = msr_read(MSR_PMG_IO_CAPTURE_ADR);  in configure_c_states()
239 	msr.lo &= ~0x7ffff;  in configure_c_states()
240 	msr.lo |= (PMB0_BASE + 4);	/* LVL_2 base address */  in configure_c_states()
241 	msr.lo |= (2 << 16);		/* CST Range: C7 is max C-state */  in configure_c_states()
242 	msr_write(MSR_PMG_IO_CAPTURE_ADR, msr);  in configure_c_states()
244 	msr = msr_read(MSR_MISC_PWR_MGMT);  in configure_c_states()
245 	msr.lo &= ~(1 << 0);	/* Enable P-state HW_ALL coordination */  in configure_c_states()
246 	msr_write(MSR_MISC_PWR_MGMT, msr);  in configure_c_states()
248 	msr = msr_read(MSR_POWER_CTL);  in configure_c_states()
249 	msr.lo |= (1 << 18);	/* Enable Energy Perf Bias MSR 0x1b0 */  in configure_c_states()
250 	msr.lo |= (1 << 1);	/* C1E Enable */  in configure_c_states()
251 	msr.lo |= (1 << 0);	/* Bi-directional PROCHOT# */  in configure_c_states()
252 	msr_write(MSR_POWER_CTL, msr);  in configure_c_states()
255 	msr.hi = 0;  in configure_c_states()
256 	msr.lo = IRTL_VALID | IRTL_1024_NS | 0x50;  in configure_c_states()
257 	msr_write(MSR_PKGC3_IRTL, msr);  in configure_c_states()
260 	msr.hi = 0;  in configure_c_states()
261 	msr.lo = IRTL_VALID | IRTL_1024_NS | 0x68;  in configure_c_states()
262 	msr_write(MSR_PKGC6_IRTL, msr);  in configure_c_states()
265 	msr.hi = 0;  in configure_c_states()
266 	msr.lo = IRTL_VALID | IRTL_1024_NS | 0x6D;  in configure_c_states()
267 	msr_write(MSR_PKGC7_IRTL, msr);  in configure_c_states()
270 	msr = msr_read(MSR_PP0_CURRENT_CONFIG);  in configure_c_states()
271 	msr.lo &= ~0x1fff;  in configure_c_states()
272 	msr.lo |= PP0_CURRENT_LIMIT;  in configure_c_states()
273 	msr_write(MSR_PP0_CURRENT_CONFIG, msr);  in configure_c_states()
276 	msr = msr_read(MSR_PP1_CURRENT_CONFIG);  in configure_c_states()
277 	msr.lo &= ~0x1fff;  in configure_c_states()
280 		msr.lo |= PP1_CURRENT_LIMIT_IVB;  in configure_c_states()
282 		msr.lo |= PP1_CURRENT_LIMIT_SNB;  in configure_c_states()
283 	msr_write(MSR_PP1_CURRENT_CONFIG, msr);  in configure_c_states()
289 	msr_t msr;  in configure_thermal_target()  local
295 	msr = msr_read(MSR_PLATFORM_INFO);  in configure_thermal_target()
296 	if ((msr.lo & (1 << 30)) && tcc_offset) {  in configure_thermal_target()
297 		msr = msr_read(MSR_TEMPERATURE_TARGET);  in configure_thermal_target()
298 		msr.lo &= ~(0xf << 24); /* Bits 27:24 */  in configure_thermal_target()
299 		msr.lo |= (tcc_offset & 0xf) << 24;  in configure_thermal_target()
300 		msr_write(MSR_TEMPERATURE_TARGET, msr);  in configure_thermal_target()
308 	msr_t msr;  in configure_misc()  local
310 	msr = msr_read(IA32_MISC_ENABLE);  in configure_misc()
311 	msr.lo |= (1 << 0);	  /* Fast String enable */  in configure_misc()
312 	msr.lo |= (1 << 3);	  /* TM1/TM2/EMTTM enable */  in configure_misc()
313 	msr.lo |= (1 << 16);	  /* Enhanced SpeedStep Enable */  in configure_misc()
314 	msr_write(IA32_MISC_ENABLE, msr);  in configure_misc()
317 	msr.lo = 0;  in configure_misc()
318 	msr.hi = 0;  in configure_misc()
319 	msr_write(IA32_THERM_INTERRUPT, msr);  in configure_misc()
322 	msr.lo = 1 << 4;  in configure_misc()
323 	msr.hi = 0;  in configure_misc()
324 	msr_write(IA32_PACKAGE_THERM_INTERRUPT, msr);  in configure_misc()
329 	msr_t msr;  in enable_lapic_tpr()  local
331 	msr = msr_read(MSR_PIC_MSG_CONTROL);  in enable_lapic_tpr()
332 	msr.lo &= ~(1 << 10);	/* Enable APIC TPR updates */  in enable_lapic_tpr()
333 	msr_write(MSR_PIC_MSG_CONTROL, msr);  in enable_lapic_tpr()
339 	msr_t msr;  in configure_dca_cap()  local
344 		msr = msr_read(IA32_PLATFORM_DCA_CAP);  in configure_dca_cap()
345 		msr.lo |= 1;  in configure_dca_cap()
346 		msr_write(IA32_PLATFORM_DCA_CAP, msr);  in configure_dca_cap()
352 	msr_t msr, perf_ctl;  in set_max_ratio()  local
359 		msr = msr_read(MSR_CONFIG_TDP_NOMINAL);  in set_max_ratio()
360 		perf_ctl.lo = (msr.lo & 0xff) << 8;  in set_max_ratio()
363 		msr = msr_read(MSR_PLATFORM_INFO);  in set_max_ratio()
364 		perf_ctl.lo = msr.lo & 0xff00;  in set_max_ratio()
374 	msr_t msr;  in set_energy_perf_bias()  local
377 	msr = msr_read(IA32_ENERGY_PERFORMANCE_BIAS);  in set_energy_perf_bias()
378 	msr.lo &= ~0xf;  in set_energy_perf_bias()
379 	msr.lo |= policy & 0xf;  in set_energy_perf_bias()
380 	msr_write(IA32_ENERGY_PERFORMANCE_BIAS, msr);  in set_energy_perf_bias()
387 	msr_t msr;  in configure_mca()  local
390 	msr.lo = 0;  in configure_mca()
391 	msr.hi = 0;  in configure_mca()
394 		msr_write(IA32_MC0_STATUS + (i * 4), msr);  in configure_mca()
455 	msr_t msr;  in model_206ax_get_info()  local
457 	msr = msr_read(MSR_IA32_PERF_CTL);  in model_206ax_get_info()
458 	info->cpu_freq = ((msr.lo >> 8) & 0xff) * SANDYBRIDGE_BCLK * 1000000;  in model_206ax_get_info()