132 	u8 reg8;  in pch_power_options()  local
181 	reg8 = inb(0x61);  in pch_power_options()
182 	reg8 &= 0x0f;		/* Higher Nibble must be 0 */  in pch_power_options()
183 	reg8 &= ~(1 << 3);	/* IOCHK# NMI Enable */  in pch_power_options()
184 	reg8 |= (1 << 2); /* PCI SERR# Disable for now */  in pch_power_options()
185 	outb(reg8, 0x61);  in pch_power_options()
187 	reg8 = inb(0x70);  in pch_power_options()
192 		reg8 &= ~(1 << 7);	/* Set NMI. */  in pch_power_options()
196 		reg8 |= (1 << 7);  in pch_power_options()
198 	outb(reg8, 0x70);  in pch_power_options()
239 	u8 reg8;  in pch_rtc_init()  local
241 	dm_pci_read_config8(pch, GEN_PMCON_3, &reg8);  in pch_rtc_init()
242 	rtc_failed = reg8 & RTC_BATTERY_DEAD;  in pch_rtc_init()
244 		reg8 &= ~RTC_BATTERY_DEAD;  in pch_rtc_init()
245 		dm_pci_write_config8(pch, GEN_PMCON_3, reg8);  in pch_rtc_init()
387 	u8 reg8;  in pch_disable_smm_only_flashing()  local
390 	dm_pci_read_config8(pch, 0xdc, &reg8);	/* BIOS_CNTL */  in pch_disable_smm_only_flashing()
391 	reg8 &= ~(1 << 5);  in pch_disable_smm_only_flashing()
392 	dm_pci_write_config8(pch, 0xdc, reg8);  in pch_disable_smm_only_flashing()