133 	u16 reg16, pmbase;  in pch_power_options()  local
150 	dm_pci_read_config16(pch, GEN_PMCON_3, &reg16);  in pch_power_options()
151 	reg16 &= 0xfffe;  in pch_power_options()
154 		reg16 |= 1;  in pch_power_options()
158 		reg16 &= ~1;  in pch_power_options()
162 		reg16 &= ~1;  in pch_power_options()
169 	reg16 &= ~(3 << 4);	/* SLP_S4# Assertion Stretch 4s */  in pch_power_options()
170 	reg16 |= (1 << 3);	/* SLP_S4# Assertion Stretch Enable */  in pch_power_options()
172 	reg16 &= ~(1 << 10);  in pch_power_options()
173 	reg16 |= (1 << 11);	/* SLP_S3# Min Assertion Width 50ms */  in pch_power_options()
175 	reg16 |= (1 << 12);	/* Disable SLP stretch after SUS well */  in pch_power_options()
177 	dm_pci_write_config16(pch, GEN_PMCON_3, reg16);  in pch_power_options()
201 	dm_pci_read_config16(pch, GEN_PMCON_1, &reg16);  in pch_power_options()
202 	reg16 &= ~(3 << 0);	/* SMI# rate 1 minute */  in pch_power_options()
203 	reg16 &= ~(1 << 10);	/* Disable BIOS_PCI_EXP_EN for native PME */  in pch_power_options()
206 	reg16 |= (3 << 0);	/* Periodic SMI every 8s */  in pch_power_options()
208 	dm_pci_write_config16(pch, GEN_PMCON_1, reg16);  in pch_power_options()
352 	u16 reg16;  in enable_clock_gating()  local
356 	dm_pci_read_config16(pch, GEN_PMCON_1, &reg16);  in enable_clock_gating()
357 	reg16 |= (1 << 2) | (1 << 11);  in enable_clock_gating()
358 	dm_pci_write_config16(pch, GEN_PMCON_1, reg16);  in enable_clock_gating()