Lines Matching +full:0 +full:xfec00000
25 #define NMI_OFF 0
27 #define ENABLE_ACPI_MODE_IN_COREBOOT 0
28 #define TEST_SMM_FLASH_LOCKDOWN 0
36 dm_pci_write_config8(pch, ACPI_CNTL, 0x80); in pch_enable_apic()
38 writel(0, IO_APIC_INDEX); in pch_enable_apic()
47 writel(0, IO_APIC_INDEX); in pch_enable_apic()
49 debug("PCH APIC ID = %x\n", (reg32 >> 24) & 0x0f); in pch_enable_apic()
56 for (i = 0; i < 3; i++) { in pch_enable_apic()
58 debug(" reg 0x%04x:", i); in pch_enable_apic()
60 debug(" 0x%08x\n", reg32); in pch_enable_apic()
69 return 0; in pch_enable_apic()
77 value = (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0); in pch_enable_serial_irqs()
107 return 0; in pch_pirq_init()
120 for (reg = 0, gpi = 0; gpi < ARRAY_SIZE(route); gpi++) in pch_gpi_routing()
123 dm_pci_write_config32(pch, 0xb8, reg); in pch_gpi_routing()
125 return 0; in pch_gpi_routing()
142 * 0 == S0 Full On in pch_power_options()
151 reg16 &= 0xfffe; in pch_power_options()
181 reg8 = inb(0x61); in pch_power_options()
182 reg8 &= 0x0f; /* Higher Nibble must be 0 */ in pch_power_options()
185 outb(reg8, 0x61); in pch_power_options()
187 reg8 = inb(0x70); in pch_power_options()
198 outb(reg8, 0x70); in pch_power_options()
202 reg16 &= ~(3 << 0); /* SMI# rate 1 minute */ in pch_power_options()
206 reg16 |= (3 << 0); /* Periodic SMI every 8s */ in pch_power_options()
215 dm_pci_read_config16(pch, 0x40, &pmbase); in pch_power_options()
216 pmbase &= 0xfffe; in pch_power_options()
218 writel(fdtdec_get_int(blob, node, "intel,gpe0-enable", 0), in pch_power_options()
220 writew(fdtdec_get_int(blob, node, "intel,alt-gp-smi-enable", 0), in pch_power_options()
224 reg32 = inl(pmbase + 0x04); /* PM1_CNT */ in pch_power_options()
226 reg32 |= (1 << 0); /* SCI_EN */ in pch_power_options()
227 outl(reg32, pmbase + 0x04); in pch_power_options()
230 setbits_le32(RCB_REG(0x3310), (1 << 4) | (1 << 5) | (1 << 0)); in pch_power_options()
231 clrbits_le32(RCB_REG(0x3f02), 0xf); in pch_power_options()
233 return 0; in pch_power_options()
247 debug("rtc_failed = 0x%x\n", rtc_failed); in pch_rtc_init()
258 dm_pci_write_config8(pch, 0xa9, 0x47); in cpt_pm_init()
259 setbits_le32(RCB_REG(0x2238), (1 << 6) | (1 << 0)); in cpt_pm_init()
261 setbits_le32(RCB_REG(0x228c), 1 << 0); in cpt_pm_init()
262 setbits_le32(RCB_REG(0x1100), (1 << 13) | (1 << 14)); in cpt_pm_init()
263 setbits_le32(RCB_REG(0x0900), 1 << 14); in cpt_pm_init()
264 writel(0xc0388400, RCB_REG(0x2304)); in cpt_pm_init()
265 setbits_le32(RCB_REG(0x2314), (1 << 5) | (1 << 18)); in cpt_pm_init()
266 setbits_le32(RCB_REG(0x2320), (1 << 15) | (1 << 1)); in cpt_pm_init()
267 clrsetbits_le32(RCB_REG(0x3314), ~0x1f, 0xf); in cpt_pm_init()
268 writel(0x050f0000, RCB_REG(0x3318)); in cpt_pm_init()
269 writel(0x04000000, RCB_REG(0x3324)); in cpt_pm_init()
270 setbits_le32(RCB_REG(0x3340), 0xfffff); in cpt_pm_init()
271 setbits_le32(RCB_REG(0x3344), 1 << 1); in cpt_pm_init()
273 writel(0x0001c000, RCB_REG(0x3360)); in cpt_pm_init()
274 writel(0x00061100, RCB_REG(0x3368)); in cpt_pm_init()
275 writel(0x7f8fdfff, RCB_REG(0x3378)); in cpt_pm_init()
276 writel(0x000003fc, RCB_REG(0x337c)); in cpt_pm_init()
277 writel(0x00001000, RCB_REG(0x3388)); in cpt_pm_init()
278 writel(0x0001c000, RCB_REG(0x3390)); in cpt_pm_init()
279 writel(0x00000800, RCB_REG(0x33a0)); in cpt_pm_init()
280 writel(0x00001000, RCB_REG(0x33b0)); in cpt_pm_init()
281 writel(0x00093900, RCB_REG(0x33c0)); in cpt_pm_init()
282 writel(0x24653002, RCB_REG(0x33cc)); in cpt_pm_init()
283 writel(0x062108fe, RCB_REG(0x33d0)); in cpt_pm_init()
284 clrsetbits_le32(RCB_REG(0x33d4), 0x0fff0fff, 0x00670060); in cpt_pm_init()
285 writel(0x01010000, RCB_REG(0x3a28)); in cpt_pm_init()
286 writel(0x01010404, RCB_REG(0x3a2c)); in cpt_pm_init()
287 writel(0x01041041, RCB_REG(0x3a80)); in cpt_pm_init()
288 clrsetbits_le32(RCB_REG(0x3a84), 0x0000ffff, 0x00001001); in cpt_pm_init()
289 setbits_le32(RCB_REG(0x3a84), 1 << 24); /* SATA 2/3 disabled */ in cpt_pm_init()
290 setbits_le32(RCB_REG(0x3a88), 1 << 0); /* SATA 4/5 disabled */ in cpt_pm_init()
291 writel(0x00000001, RCB_REG(0x3a6c)); in cpt_pm_init()
292 clrsetbits_le32(RCB_REG(0x2344), ~0x00ffff00, 0xff00000c); in cpt_pm_init()
293 clrsetbits_le32(RCB_REG(0x80c), 0xff << 20, 0x11 << 20); in cpt_pm_init()
294 writel(0, RCB_REG(0x33c8)); in cpt_pm_init()
295 setbits_le32(RCB_REG(0x21b0), 0xf); in cpt_pm_init()
302 dm_pci_write_config8(pch, 0xa9, 0x47); in ppt_pm_init()
303 setbits_le32(RCB_REG(0x2238), 1 << 0); in ppt_pm_init()
304 setbits_le32(RCB_REG(0x228c), 1 << 0); in ppt_pm_init()
305 setbits_le16(RCB_REG(0x1100), (1 << 13) | (1 << 14)); in ppt_pm_init()
306 setbits_le16(RCB_REG(0x0900), 1 << 14); in ppt_pm_init()
307 writel(0xc03b8400, RCB_REG(0x2304)); in ppt_pm_init()
308 setbits_le32(RCB_REG(0x2314), (1 << 5) | (1 << 18)); in ppt_pm_init()
309 setbits_le32(RCB_REG(0x2320), (1 << 15) | (1 << 1)); in ppt_pm_init()
310 clrsetbits_le32(RCB_REG(0x3314), 0x1f, 0xf); in ppt_pm_init()
311 writel(0x054f0000, RCB_REG(0x3318)); in ppt_pm_init()
312 writel(0x04000000, RCB_REG(0x3324)); in ppt_pm_init()
313 setbits_le32(RCB_REG(0x3340), 0xfffff); in ppt_pm_init()
314 setbits_le32(RCB_REG(0x3344), (1 << 1) | (1 << 0)); in ppt_pm_init()
315 writel(0x0001c000, RCB_REG(0x3360)); in ppt_pm_init()
316 writel(0x00061100, RCB_REG(0x3368)); in ppt_pm_init()
317 writel(0x7f8fdfff, RCB_REG(0x3378)); in ppt_pm_init()
318 writel(0x000003fd, RCB_REG(0x337c)); in ppt_pm_init()
319 writel(0x00001000, RCB_REG(0x3388)); in ppt_pm_init()
320 writel(0x0001c000, RCB_REG(0x3390)); in ppt_pm_init()
321 writel(0x00000800, RCB_REG(0x33a0)); in ppt_pm_init()
322 writel(0x00001000, RCB_REG(0x33b0)); in ppt_pm_init()
323 writel(0x00093900, RCB_REG(0x33c0)); in ppt_pm_init()
324 writel(0x24653002, RCB_REG(0x33cc)); in ppt_pm_init()
325 writel(0x067388fe, RCB_REG(0x33d0)); in ppt_pm_init()
326 clrsetbits_le32(RCB_REG(0x33d4), 0x0fff0fff, 0x00670060); in ppt_pm_init()
327 writel(0x01010000, RCB_REG(0x3a28)); in ppt_pm_init()
328 writel(0x01010404, RCB_REG(0x3a2c)); in ppt_pm_init()
329 writel(0x01040000, RCB_REG(0x3a80)); in ppt_pm_init()
330 clrsetbits_le32(RCB_REG(0x3a84), 0x0000ffff, 0x00001001); in ppt_pm_init()
332 setbits_le32(RCB_REG(0x3a84), 1 << 24); in ppt_pm_init()
334 setbits_le32(RCB_REG(0x3a88), 1 << 0); in ppt_pm_init()
335 writel(0x00000001, RCB_REG(0x3a6c)); in ppt_pm_init()
336 clrsetbits_le32(RCB_REG(0x2344), 0xff0000ff, 0xff00000c); in ppt_pm_init()
337 clrsetbits_le32(RCB_REG(0x80c), 0xff << 20, 0x11 << 20); in ppt_pm_init()
338 setbits_le32(RCB_REG(0x33a4), (1 << 0)); in ppt_pm_init()
339 writel(0, RCB_REG(0x33c8)); in ppt_pm_init()
340 setbits_le32(RCB_REG(0x21b0), 0xf); in ppt_pm_init()
345 /* Move HPET to default address 0xfed00000 and enable it */ in enable_hpet()
346 clrsetbits_le32(RCB_REG(HPTC), 3 << 0, 1 << 7); in enable_hpet()
354 setbits_le32(RCB_REG(0x2234), 0xf); in enable_clock_gating()
360 pch_iobp_update(pch, 0xeb007f07, ~0U, 1 << 31); in enable_clock_gating()
361 pch_iobp_update(pch, 0xeb004000, ~0U, 1 << 7); in enable_clock_gating()
362 pch_iobp_update(pch, 0xec007f07, ~0U, 1 << 31); in enable_clock_gating()
363 pch_iobp_update(pch, 0xec004000, ~0U, 1 << 7); in enable_clock_gating()
376 reg32 |= (1 << 0); in enable_clock_gating()
377 reg32 |= (0xf << 1); in enable_clock_gating()
380 setbits_le32(RCB_REG(0x38c0), 0x7); in enable_clock_gating()
381 setbits_le32(RCB_REG(0x36d4), 0x6680c004); in enable_clock_gating()
382 setbits_le32(RCB_REG(0x3564), 0x3); in enable_clock_gating()
390 dm_pci_read_config8(pch, 0xdc, ®8); /* BIOS_CNTL */ in pch_disable_smm_only_flashing()
392 dm_pci_write_config8(pch, 0xdc, reg8); in pch_disable_smm_only_flashing()
405 clrbits_le32(RCB_REG(0x2304), 1 << 10); in pch_fixups()
406 setbits_le32(RCB_REG(0x21a4), (1 << 11) | (1 << 10)); in pch_fixups()
407 setbits_le32(RCB_REG(0x21a8), 0x3); in pch_fixups()
414 /* Observe SPI Descriptor Component Section 0 */ in set_spi_speed()
415 writel(0x1000, RCB_REG(SPI_DESC_COMP0)); in set_spi_speed()
431 dm_pci_write_bar32(pch, 0, 0); in lpc_init_extra()
432 dm_pci_write_bar32(pch, 1, 0xff800000); in lpc_init_extra()
433 dm_pci_write_bar32(pch, 2, 0xfec00000); in lpc_init_extra()
434 dm_pci_write_bar32(pch, 3, 0x800); in lpc_init_extra()
435 dm_pci_write_bar32(pch, 4, 0x900); in lpc_init_extra()
438 dm_pci_write_config16(pch, PCI_COMMAND, 0x000f); in lpc_init_extra()
477 return 0; in lpc_init_extra()
491 dm_pci_write_config8(dev->parent, ACPI_CNTL, 0x80); in bd82x6x_lpc_early_init()
495 outw(1 << 11, DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */ in bd82x6x_lpc_early_init()
498 dm_pci_write_config32(dev->parent, GPIO_CNTL, 0x10); in bd82x6x_lpc_early_init()
500 return 0; in bd82x6x_lpc_early_init()