Lines Matching refs:movl
47 movl $0x000C4500, %eax
48 movl $0xFEE00300, %esi
49 movl %eax, (%esi)
52 movl $MSR_IA32_UCODE_WRITE, %ecx
54 movl $_dt_ucode_base_size, %eax
55 movl (%eax), %eax
61 movl $mtrr_table, %esi
62 movl $((mtrr_table_end - mtrr_table) / 2), %edi
75 movl $MTRR_DEF_TYPE_MSR, %ecx
82 movl $(MTRR_PHYS_BASE_MSR(0)), %ecx
83 movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax
89 movl $(MTRR_PHYS_MASK_MSR(0)), %ecx
90 movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
91 movl $CPU_PHYSMASK_HI, %edx
97 movl $MTRR_DEF_TYPE_MSR, %ecx
103 movl %cr0, %eax
106 movl %eax, %cr0
109 movl $NOEVICTMOD_MSR, %ecx
116 movl $CACHE_AS_RAM_BASE, %esi
117 movl %esi, %edi
118 movl $(CACHE_AS_RAM_SIZE / 4), %ecx
123 movl $NOEVICTMOD_MSR, %ecx
130 movl %cr0, %eax
132 movl %eax, %cr0
135 movl $MTRR_PHYS_BASE_MSR(1), %ecx
137 movl $car_init_ret, %eax
142 movl $MTRR_PHYS_MASK_MSR(1), %ecx
143 movl $CPU_PHYSMASK_HI, %edx
144 movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
150 movl $MTRR_PHYS_BASE_MSR(2), %ecx
151 movl $(CACHE_MRC_BASE | MTRR_TYPE_WRPROT), %eax
154 movl $MTRR_PHYS_MASK_MSR(2), %ecx
155 movl $(CACHE_MRC_MASK | MTRR_PHYS_MASK_VALID), %eax
156 movl $CPU_PHYSMASK_HI, %edx
162 movl %cr0, %eax
164 movl %eax, %cr0
170 movl (%esi), %eax
180 movl %cr0, %eax
182 movl %eax, %cr0
185 movl $MTRR_DEF_TYPE_MSR, %ecx
191 movl $NOEVICTMOD_MSR, %ecx
207 movl $MTRR_PHYS_BASE_MSR(2), %ecx
209 movl $MTRR_PHYS_MASK_MSR(2), %ecx
214 movl $MTRR_DEF_TYPE_MSR, %ecx