121 	msr_write(IA32_PERF_CTL, perf_ctl);  in set_max_freq()
249 	msr_write(MSR_VR_CURRENT_CONFIG, msr);  in initialize_vr_config()
283 	msr_write(MSR_VR_MISC_CONFIG, msr);  in initialize_vr_config()
296 	msr_write(MSR_VR_MISC_CONFIG2, msr);  in initialize_vr_config()
427 	msr_write(IA32_PERF_CTL, perf_ctl);  in set_max_ratio()
475 		msr_write(MSR_IA32_MC0_STATUS + (i * 4), msr);  in configure_mca()
484 	msr_write(MSR_PIC_MSG_CONTROL, msr);  in enable_lapic_tpr()
502 	msr_write(MSR_PMG_CST_CONFIG_CONTROL, msr);  in configure_c_states()
506 	msr_write(MSR_MISC_PWR_MGMT, msr);  in configure_c_states()
512 	msr_write(MSR_POWER_CTL, msr);  in configure_c_states()
517 	msr_write(MSR_C_STATE_LATENCY_CONTROL_0, msr);  in configure_c_states()
522 	msr_write(MSR_C_STATE_LATENCY_CONTROL_1, msr);  in configure_c_states()
527 	msr_write(MSR_C_STATE_LATENCY_CONTROL_2, msr);  in configure_c_states()
532 	msr_write(MSR_C_STATE_LATENCY_CONTROL_3, msr);  in configure_c_states()
537 	msr_write(MSR_C_STATE_LATENCY_CONTROL_4, msr);  in configure_c_states()
542 	msr_write(MSR_C_STATE_LATENCY_CONTROL_5, msr);  in configure_c_states()
553 	msr_write(MSR_IA32_MISC_ENABLE, msr);  in configure_misc()
558 	msr_write(MSR_IA32_THERM_INTERRUPT, msr);  in configure_misc()
563 	msr_write(MSR_IA32_PACKAGE_THERM_INTERRUPT, msr);  in configure_misc()
580 		msr_write(MSR_TEMPERATURE_TARGET, msr);  in configure_thermal_target()
594 		msr_write(MSR_IA32_PLATFORM_DCA_CAP, msr);  in configure_dca_cap()
612 	msr_write(MSR_IA32_ENERGY_PERFORMANCE_BIAS, msr);  in set_energy_perf_bias()
701 	msr_write(MSR_PKG_POWER_LIMIT, limit);  in cpu_set_power_limits()
710 	msr_write(MSR_DDR_RAPL_LIMIT, msr);  in cpu_set_power_limits()
717 		msr_write(MSR_TURBO_ACTIVATION_RATIO, limit);  in cpu_set_power_limits()