4  * SPDX-License-Identifier:	GPL-2.0
95 		return -ENODEV;  in arch_cpu_init_dm()
143 	gd->arch.pei_boot_mode = PEI_BOOT_NONE;  in checkcpu()
161  * The core 100MHz BLCK is disabled in deeper c-states. One needs to calibrate
177 	} while (wait_count < 1000);  in pcode_ready()
179 	return -ETIMEDOUT;  in pcode_ready()
244 	msr.hi |= (0x01 << (52 - 32)); /* PSI3 threshold -  1A */  in initialize_vr_config()
245 	msr.hi |= (0x05 << (42 - 32)); /* PSI2 threshold -  5A */  in initialize_vr_config()
246 	msr.hi |= (0x14 << (32 - 32)); /* PSI1 threshold - 20A */  in initialize_vr_config()
247 	msr.hi |= (1 <<  (62 - 32)); /* Enable PSI4 */  in initialize_vr_config()
254 	msr.hi &= ~(0x3ff << (40 - 32));  in initialize_vr_config()
255 	msr.hi |= (0x200 << (40 - 32)); /* 1.0 */  in initialize_vr_config()
259 	msr.hi &= ~(1 << (51 - 32));  in initialize_vr_config()
260 	/* Enable decay mode on C-state entry */  in initialize_vr_config()
261 	msr.hi |= (1 << (52 - 32));  in initialize_vr_config()
263 	msr.hi &= ~(0x3 << (53 - 32));  in initialize_vr_config()
264 	/* Configure the C-state exit ramp rate */  in initialize_vr_config()
265 	ramp = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),  in initialize_vr_config()
266 			      "intel,slow-ramp", -1);  in initialize_vr_config()
267 	if (ramp != -1) {  in initialize_vr_config()
269 		msr.hi |= ((ramp & 0x3) << (53 - 32));  in initialize_vr_config()
271 		msr.hi &= ~(1 << (50 - 32));  in initialize_vr_config()
274 		msr.hi |= (0x01 << (53 - 32));  in initialize_vr_config()
276 		msr.hi |= (1 << (50 - 32));  in initialize_vr_config()
280 	min_vid = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),  in initialize_vr_config()
281 				 "intel,min-vid", 0);  in initialize_vr_config()
311 	/* A non-zero value initiates the PCODE calibration */  in calibrate_24mhz_bclk()
447 	priv->ht_disabled = num_threads == num_cores;  in broadwell_init()
494 	msr.lo |= (1 << 30);	/* Package c-state Undemotion Enable */  in configure_c_states()
495 	msr.lo |= (1 << 29);	/* Package c-state Demotion Enable */  in configure_c_states()
501 	/* The deepest package c-state defaults to factory-configured value */  in configure_c_states()
505 	msr.lo &= ~(1 << 0);	/* Enable P-state HW_ALL coordination */  in configure_c_states()
511 	msr.lo |= (1 << 0);	/* Bi-directional PROCHOT# */  in configure_c_states()
514 	/* C-state Interrupt Response Latency Control 0 - package C3 latency */  in configure_c_states()
519 	/* C-state Interrupt Response Latency Control 1 */  in configure_c_states()
524 	/* C-state Interrupt Response Latency Control 2 - package C6/C7 short */  in configure_c_states()
529 	/* C-state Interrupt Response Latency Control 3 - package C8 */  in configure_c_states()
534 	/* C-state Interrupt Response Latency Control 4 - package C9 */  in configure_c_states()
539 	/* C-state Interrupt Response Latency Control 5 - package C10 */  in configure_c_states()
571 	tcc_offset = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),  in configure_thermal_target()
572 				    "intel,tcc-offset", 0);  in configure_thermal_target()
589 	/* Check feature flag in CPUID.(EAX=1):ECX[18]==1 */  in configure_dca_cap()
591 	if (cpuid_regs.ecx & (1 << 18)) {  in configure_dca_cap()
601 	int ecx;  in set_energy_perf_bias()  local
604 	ecx = cpuid_ecx(0x6);  in set_energy_perf_bias()
605 	if (!(ecx & (1 << 3)))  in set_energy_perf_bias()
666 	power_unit = 2 << ((msr.lo & 0xf) - 1);  in cpu_set_power_limits()
726 	info->cpu_freq = ((msr.lo >> 8) & 0xff) * BROADWELL_BCLK * 1000000;  in broadwell_get_info()
727 	info->features = 1 << CPU_FEAT_L1_CACHE | 1 << CPU_FEAT_MMU |  in broadwell_get_info()
740 	if (dev->seq == 0) {  in cpu_x86_broadwell_probe()
756 	{ .compatible = "intel,core-i3-gen5" },