Lines Matching +full:0 +full:xff000044

10 #define CCR		0xFF00001C
11 #define WTCNT		0xFFCC0000
12 #define CCR_CACHE_INIT	0x0000090b
21 #define MMU_BASE	((struct mmu_regs *)0xff000000)
24 #define WTCSR0		0xffcc0002
25 #define WRSTCSR_R	0xffcc0003
26 #define WRSTCSR_W	0xffcc0002
27 #define WTCSR_PREFIX		0xa500
28 #define WRSTCSR_PREFIX		0x6900
29 #define WRSTCSR_WOVF_PREFIX	0x9600
32 #define SCIF0_BASE	0xfe4b0000	/* The real name is SCIF2 */
33 #define SCIF1_BASE	0xfe4c0000	/* The real name is SCIF3 */
34 #define SCIF2_BASE	0xfe4d0000	/* The real name is SCIF4 */
37 #define SMR0		0xfe470000
40 #define TMU_BASE    0xFE430000
49 #define GETHER0_MAC_BASE	((struct ether_mac_regs *)0xfee0400)
50 #define GETHER1_MAC_BASE	((struct ether_mac_regs *)0xfee0c00)
51 #define ETHER0_MAC_BASE		((struct ether_mac_regs *)0xfef0000)
52 #define ETHER1_MAC_BASE		((struct ether_mac_regs *)0xfef0800)
58 #define GETHER_CONTROL_BASE	((struct gether_control_regs *)0xffc10100)
59 #define GBECONT_RMII1		0x00020000
60 #define GBECONT_RMII0		0x00010000
67 #define USB0_COMMON_BASE	((struct usb_common_regs *)0xfe450000)
68 #define USB1_COMMON_BASE	((struct usb_common_regs *)0xfe4f0000)
75 #define USB0_PHY_BASE		((struct usb0_phy_regs *)0xfe5f0000)
82 #define USB1_PORT_BASE		((struct usb1_port_regs *)0xfe4f2000)
85 	unsigned int	ehcidatac;	/* 0xfe4fe018 */
89 #define USB1_ALIGNMENT_BASE	((struct usb1_alignment_regs *)0xfe4fe018)
110 #define GCTRL_BASE		((struct gctrl_regs *)0xffc10000)
157 #define PCIE_SETUP_BASE		((struct pcie_setup_regs *)0xffca1000)
164 #define PCIE_SYSTEM_BUS_BASE	((struct pcie_system_bus_regs *)0xffca1600)
177 #define PCIEBRG_BASE		((struct pciebrg_regs *)0xffd60000)
180 #define CCN_PRR			0xff000044
181 #define prr_mask(_val)		((_val >> 4) & 0xff)
182 #define PRR_SH7757_B0		0x10
183 #define PRR_SH7757_C0		0x11