Lines Matching refs:uint
18 uint sc_siumcr;
19 uint sc_sypcr;
20 uint sc_swt;
23 uint sc_sipend;
24 uint sc_simask;
25 uint sc_siel;
26 uint sc_sivec;
27 uint sc_tesr;
29 uint sc_sdcr;
36 uint pcmc_pbr0;
37 uint pcmc_por0;
38 uint pcmc_pbr1;
39 uint pcmc_por1;
40 uint pcmc_pbr2;
41 uint pcmc_por2;
42 uint pcmc_pbr3;
43 uint pcmc_por3;
44 uint pcmc_pbr4;
45 uint pcmc_por4;
46 uint pcmc_pbr5;
47 uint pcmc_por5;
48 uint pcmc_pbr6;
49 uint pcmc_por6;
50 uint pcmc_pbr7;
51 uint pcmc_por7;
53 uint pcmc_pgcra;
54 uint pcmc_pgcrb;
55 uint pcmc_pscr;
57 uint pcmc_pipr;
59 uint pcmc_per;
66 uint memc_br0;
67 uint memc_or0;
68 uint memc_br1;
69 uint memc_or1;
70 uint memc_br2;
71 uint memc_or2;
72 uint memc_br3;
73 uint memc_or3;
74 uint memc_br4;
75 uint memc_or4;
76 uint memc_br5;
77 uint memc_or5;
78 uint memc_br6;
79 uint memc_or6;
80 uint memc_br7;
81 uint memc_or7;
83 uint memc_mar;
84 uint memc_mcr;
86 uint memc_mamr;
87 uint memc_mbmr;
90 uint memc_mdr;
99 uint sit_tbreff0;
100 uint sit_tbreff1;
104 uint sit_rtc;
105 uint sit_rtsec;
106 uint sit_rtcal;
110 uint sit_pitc;
111 uint sit_pitr;
141 uint car_sccr;
142 uint car_plprcr;
143 uint car_rsr;
150 uint sitk_tbscrk;
151 uint sitk_tbreff0k;
152 uint sitk_tbreff1k;
153 uint sitk_tbk;
155 uint sitk_rtcsck;
156 uint sitk_rtck;
157 uint sitk_rtseck;
158 uint sitk_rtcalk;
160 uint sitk_piscrk;
161 uint sitk_pitck;
168 uint cark_sccrk;
169 uint cark_plprcrk;
170 uint cark_rsrk;
199 uint sdma_sdar;
219 uint cpic_cicr;
220 uint cpic_cipr;
221 uint cpic_cimr;
222 uint cpic_cisr;
243 uint utmode;
278 uint scc_gsmrl;
279 uint scc_gsmrh;
307 uint fec_addr_low; /* lower 32 bits of station address */
310 uint fec_hash_table_high; /* upper 32-bits of hash table */
311 uint fec_hash_table_low; /* lower 32-bits of hash table */
312 uint fec_r_des_start; /* beginning of Rx descriptor ring */
313 uint fec_x_des_start; /* beginning of Tx descriptor ring */
314 uint fec_r_buff_size; /* Rx buffer size */
315 uint res2[9]; /* reserved */
316 uint fec_ecntrl; /* ethernet control register */
317 uint fec_ievent; /* interrupt event register */
318 uint fec_imask; /* interrupt mask register */
319 uint fec_ivec; /* interrupt level and vector status */
320 uint fec_r_des_active; /* Rx ring updated flag */
321 uint fec_x_des_active; /* Tx ring updated flag */
322 uint res3[10]; /* reserved */
323 uint fec_mii_data; /* MII data register */
324 uint fec_mii_speed; /* MII speed control register */
325 uint res4[17]; /* reserved */
326 uint fec_r_bound; /* end of RAM (read-only) */
327 uint fec_r_fstart; /* Rx FIFO start address */
328 uint res5[6]; /* reserved */
329 uint fec_x_fstart; /* Tx FIFO start address */
330 uint res6[17]; /* reserved */
331 uint fec_fun_code; /* fec SDMA function code */
332 uint res7[3]; /* reserved */
333 uint fec_r_cntrl; /* Rx control register */
334 uint fec_r_hash; /* Rx hash register */
335 uint res8[14]; /* reserved */
336 uint fec_x_cntrl; /* Tx control register */
337 uint res9[0x1e]; /* reserved */
361 uint cp_brgc1;
362 uint cp_brgc2;
363 uint cp_brgc3;
364 uint cp_brgc4;
391 uint cp_pbdir;
392 uint cp_pbpar;
395 uint cp_pbdat;
399 uint cp_pedir;
400 uint cp_pepar;
401 uint cp_peso;
402 uint cp_peodr;
403 uint cp_pedat;
408 uint cp_cptr;
412 uint cp_simode;
418 uint cp_sicr;
419 uint cp_sirp;