Lines Matching +full:0 +full:x31000
29 #define CCSRAR_C 0x80000000 /* Commit */
38 u8 res3[0xbd4];
45 u8 res35[0x204];
58 u32 lawbar0; /* Local Access Window 0 Base Addr */
60 u32 lawar0; /* Local Access Window 0 Attrs */
118 #define DDR_EOR_RD_BDW_OPT_DIS 0x80000000 /* Read BDW Opt. disable */
119 #define DDR_EOR_ADDR_HASH_EN 0x40000000 /* Address hash enabled */
178 u32 csmode[4]; /* 0x2c: sSPI CS0/1/2/3 mode */
179 u8 res2[4048]; /* fill up to 0x1000 */
192 u32 potar0; /* PCIX Outbound Transaction Addr 0 */
193 u32 potear0; /* PCIX Outbound Translation Extended Addr 0 */
194 u32 powbar0; /* PCIX Outbound Window Base Addr 0 */
195 u32 powbear0; /* PCIX Outbound Window Base Extended Addr 0 */
196 u32 powar0; /* PCIX Outbound Window Attrs 0 */
252 #define PCIX_COMMAND 0x62
253 #define POWAR_EN 0x80000000
254 #define POWAR_IO_READ 0x00080000
255 #define POWAR_MEM_READ 0x00040000
256 #define POWAR_IO_WRITE 0x00008000
257 #define POWAR_MEM_WRITE 0x00004000
258 #define POWAR_MEM_512M 0x0000001c
259 #define POWAR_IO_1M 0x00000013
261 #define PIWAR_EN 0x80000000
262 #define PIWAR_PF 0x20000000
263 #define PIWAR_LOCAL 0x00f00000
264 #define PIWAR_READ_SNOOP 0x00050000
265 #define PIWAR_WRITE_SNOOP 0x00005000
266 #define PIWAR_MEM_2G 0x0000001e
281 u32 l2ctl; /* L2 configuration 0 */
283 u32 l2cewar0; /* L2 cache external write addr 0 */
285 u32 l2cewcr0; /* L2 cache external write control 0 */
299 u32 l2srbar0; /* L2 memory-mapped SRAM base addr 0 */
321 #define MPC85xx_L2CTL_L2E 0x80000000
322 #define MPC85xx_L2CTL_L2SRAM_ENTIRE 0x00010000
323 #define MPC85xx_L2ERRDIS_MBECC 0x00000008
324 #define MPC85xx_L2ERRDIS_SBECC 0x00000004
385 u32 rbptrh; /* RX Buffer Desc Ptr High 0 */
394 u32 rbaseh; /* RX Desc Base Addr High 0 */
469 u32 iaddr0; /* Indivdual addr 0 */
478 u32 gaddr0; /* Global addr 0 */
624 u32 ipidr0; /* Interprocessor IRQ Dispatch 0 */
643 #define MPC85xx_PICGCR_RST 0x80000000
644 #define MPC85xx_PICGCR_M 0x20000000
650 u32 ipivpr0; /* IPI Vector/Priority 0 */
662 u32 gtccr0; /* Global Timer Current Count 0 */
664 u32 gtbcr0; /* Global Timer Base Count 0 */
666 u32 gtvpr0; /* Global Timer Vector/Priority 0 */
668 u32 gtdr0; /* Global Timer Destination 0 */
696 u32 irqsr0; /* IRQ_OUT Summary 0 */
700 u32 cisr0; /* Critical IRQ Summary 0 */
704 u32 msgr0; /* Message 0 */
716 u32 eivpr0; /* External IRQ Vector/Priority 0 */
718 u32 eidr0; /* External IRQ Destination 0 */
764 u32 iivpr0; /* Internal IRQ Vector/Priority 0 */
766 u32 iidr0; /* Internal IRQ Destination 0 */
892 u32 mivpr0; /* Messaging IRQ Vector/Priority 0 */
894 u32 midr0; /* Messaging IRQ Destination 0 */
908 u32 ipi0dr0; /* Processor 0 Interprocessor IRQ Dispatch 0 */
910 u32 ipi0dr1; /* Processor 0 Interprocessor IRQ Dispatch 1 */
912 u32 ipi0dr2; /* Processor 0 Interprocessor IRQ Dispatch 2 */
914 u32 ipi0dr3; /* Processor 0 Interprocessor IRQ Dispatch 3 */
916 u32 ctpr0; /* Current Task Priority for Processor 0 */
918 u32 whoami0; /* Who Am I for Processor 0 */
920 u32 iack0; /* IRQ Acknowledge for Processor 0 */
922 u32 eoi0; /* End Of IRQ for Processor 0 */
1286 u32 pmbh0csr; /* Port Maintenance Block Header 0 CSR */
1312 u32 pcseccsr0; /* Port packet/control symbol ECCSR 0 */
1352 u32 a0txcr; /* Port Arbitration 0 Tx CR */
1519 u32 cpcewcr0; /* External Write reg 0 */
1520 u32 cpcewabr0; /* External write base reg 0 */
1526 u32 cpcsrcr0; /* SRAM control reg 0 */
1551 u32 cpchdbcr0; /* hardware debug control register 0 */
1555 #define CPC_CSR0_CE 0x80000000 /* Cache Enable */
1556 #define CPC_CSR0_PE 0x40000000 /* Enable ECC */
1557 #define CPC_CSR0_FI 0x00200000 /* Cache Flash Invalidate */
1558 #define CPC_CSR0_WT 0x00080000 /* Write-through mode */
1559 #define CPC_CSR0_FL 0x00000800 /* Hardware cache flush */
1560 #define CPC_CSR0_LFC 0x00000400 /* Cache Lock Flash Clear */
1561 #define CPC_CFG0_SZ_MASK 0x00003fff
1563 #define CPC_CFG0_NUM_WAYS(x) (((x >> 14) & 0x1f) + 1)
1564 #define CPC_CFG0_LINE_SZ(x) ((((x >> 23) & 0x3) + 1) * 32)
1565 #define CPC_SRCR1_SRBARU_MASK 0x0000ffff
1568 #define CPC_SRCR0_SRBARL_MASK 0xffff8000
1570 #define CPC_SRCR0_INTLVEN 0x00000100
1571 #define CPC_SRCR0_SRAMSZ_1_WAY 0x00000000
1572 #define CPC_SRCR0_SRAMSZ_2_WAY 0x00000002
1573 #define CPC_SRCR0_SRAMSZ_4_WAY 0x00000004
1574 #define CPC_SRCR0_SRAMSZ_8_WAY 0x00000006
1575 #define CPC_SRCR0_SRAMSZ_16_WAY 0x00000008
1576 #define CPC_SRCR0_SRAMSZ_32_WAY 0x0000000a
1577 #define CPC_SRCR0_SRAMEN 0x00000001
1578 #define CPC_ERRDIS_TMHITDIS 0x00000080 /* multi-way hit disable */
1579 #define CPC_HDBCR0_CDQ_SPEC_DIS 0x08000000
1580 #define CPC_HDBCR0_TAG_ECC_SCRUB_DIS 0x01000000
1581 #define CPC_HDBCR0_DATA_ECC_SCRUB_DIS 0x00400000
1582 #define CPC_HDBCR0_SPLRU_LEVEL_EN 0x001e0000
1592 #define FSL_DCFG_PORSR1_SYSCLK_MASK 0x1
1593 #define FSL_DCFG_PORSR1_SYSCLK_SINGLE_ENDED 0x1
1594 #define FSL_DCFG_PORSR1_SYSCLK_DIFF 0x0
1596 u8 res_008[0x20-0x8];
1601 #define FSL_CORENET_DCFG_FUSESR_VID_MASK 0x1F
1603 #define FSL_CORENET_DCFG_FUSESR_ALTVID_MASK 0x1F
1604 u8 res_02c[0x70-0x2c];
1611 #define FSL_CORENET_DEVDISR_PBL 0x80000000
1612 #define FSL_CORENET_DEVDISR_PMAN 0x40000000
1613 #define FSL_CORENET_DEVDISR_ESDHC 0x20000000
1614 #define FSL_CORENET_DEVDISR_DMA1 0x00800000
1615 #define FSL_CORENET_DEVDISR_DMA2 0x00400000
1616 #define FSL_CORENET_DEVDISR_USB1 0x00080000
1617 #define FSL_CORENET_DEVDISR_USB2 0x00040000
1618 #define FSL_CORENET_DEVDISR_SATA1 0x00008000
1619 #define FSL_CORENET_DEVDISR_SATA2 0x00004000
1620 #define FSL_CORENET_DEVDISR_PME 0x00000800
1621 #define FSL_CORENET_DEVDISR_SEC 0x00000200
1622 #define FSL_CORENET_DEVDISR_RMU 0x00000080
1623 #define FSL_CORENET_DEVDISR_DCE 0x00000040
1624 #define FSL_CORENET_DEVDISR2_DTSEC1_1 0x80000000
1625 #define FSL_CORENET_DEVDISR2_DTSEC1_2 0x40000000
1626 #define FSL_CORENET_DEVDISR2_DTSEC1_3 0x20000000
1627 #define FSL_CORENET_DEVDISR2_DTSEC1_4 0x10000000
1628 #define FSL_CORENET_DEVDISR2_DTSEC1_5 0x08000000
1629 #define FSL_CORENET_DEVDISR2_DTSEC1_6 0x04000000
1630 #define FSL_CORENET_DEVDISR2_DTSEC1_9 0x00800000
1631 #define FSL_CORENET_DEVDISR2_DTSEC1_10 0x00400000
1633 #define FSL_CORENET_DEVDISR2_10GEC1_1 0x80000000
1634 #define FSL_CORENET_DEVDISR2_10GEC1_2 0x40000000
1636 #define FSL_CORENET_DEVDISR2_10GEC1_1 0x00800000
1637 #define FSL_CORENET_DEVDISR2_10GEC1_2 0x00400000
1638 #define FSL_CORENET_DEVDISR2_10GEC1_3 0x80000000
1639 #define FSL_CORENET_DEVDISR2_10GEC1_4 0x40000000
1641 #define FSL_CORENET_DEVDISR2_DTSEC2_1 0x00080000
1642 #define FSL_CORENET_DEVDISR2_DTSEC2_2 0x00040000
1643 #define FSL_CORENET_DEVDISR2_DTSEC2_3 0x00020000
1644 #define FSL_CORENET_DEVDISR2_DTSEC2_4 0x00010000
1645 #define FSL_CORENET_DEVDISR2_DTSEC2_5 0x00008000
1646 #define FSL_CORENET_DEVDISR2_DTSEC2_6 0x00004000
1647 #define FSL_CORENET_DEVDISR2_DTSEC2_9 0x00000800
1648 #define FSL_CORENET_DEVDISR2_DTSEC2_10 0x00000400
1649 #define FSL_CORENET_DEVDISR2_10GEC2_1 0x00000800
1650 #define FSL_CORENET_DEVDISR2_10GEC2_2 0x00000400
1651 #define FSL_CORENET_DEVDISR2_FM1 0x00000080
1652 #define FSL_CORENET_DEVDISR2_FM2 0x00000040
1653 #define FSL_CORENET_DEVDISR2_CPRI 0x00000008
1654 #define FSL_CORENET_DEVDISR3_PCIE1 0x80000000
1655 #define FSL_CORENET_DEVDISR3_PCIE2 0x40000000
1656 #define FSL_CORENET_DEVDISR3_PCIE3 0x20000000
1657 #define FSL_CORENET_DEVDISR3_PCIE4 0x10000000
1658 #define FSL_CORENET_DEVDISR3_SRIO1 0x08000000
1659 #define FSL_CORENET_DEVDISR3_SRIO2 0x04000000
1660 #define FSL_CORENET_DEVDISR3_QMAN 0x00080000
1661 #define FSL_CORENET_DEVDISR3_BMAN 0x00040000
1662 #define FSL_CORENET_DEVDISR3_LA1 0x00008000
1663 #define FSL_CORENET_DEVDISR3_MAPLE1 0x00000800
1664 #define FSL_CORENET_DEVDISR3_MAPLE2 0x00000400
1665 #define FSL_CORENET_DEVDISR3_MAPLE3 0x00000200
1666 #define FSL_CORENET_DEVDISR4_I2C1 0x80000000
1667 #define FSL_CORENET_DEVDISR4_I2C2 0x40000000
1668 #define FSL_CORENET_DEVDISR4_DUART1 0x20000000
1669 #define FSL_CORENET_DEVDISR4_DUART2 0x10000000
1670 #define FSL_CORENET_DEVDISR4_ESPI 0x08000000
1671 #define FSL_CORENET_DEVDISR5_DDR1 0x80000000
1672 #define FSL_CORENET_DEVDISR5_DDR2 0x40000000
1673 #define FSL_CORENET_DEVDISR5_DDR3 0x20000000
1674 #define FSL_CORENET_DEVDISR5_CPC1 0x08000000
1675 #define FSL_CORENET_DEVDISR5_CPC2 0x04000000
1676 #define FSL_CORENET_DEVDISR5_CPC3 0x02000000
1677 #define FSL_CORENET_DEVDISR5_IFC 0x00800000
1678 #define FSL_CORENET_DEVDISR5_GPIO 0x00400000
1679 #define FSL_CORENET_DEVDISR5_DBG 0x00200000
1680 #define FSL_CORENET_DEVDISR5_NAL 0x00100000
1681 #define FSL_CORENET_DEVDISR5_TIMERS 0x00020000
1684 #define FSL_CORENET_DEVDISR_PCIE1 0x80000000
1685 #define FSL_CORENET_DEVDISR_PCIE2 0x40000000
1686 #define FSL_CORENET_DEVDISR_PCIE3 0x20000000
1687 #define FSL_CORENET_DEVDISR_PCIE4 0x10000000
1688 #define FSL_CORENET_DEVDISR_RMU 0x08000000
1689 #define FSL_CORENET_DEVDISR_SRIO1 0x04000000
1690 #define FSL_CORENET_DEVDISR_SRIO2 0x02000000
1691 #define FSL_CORENET_DEVDISR_DMA1 0x00400000
1692 #define FSL_CORENET_DEVDISR_DMA2 0x00200000
1693 #define FSL_CORENET_DEVDISR_DDR1 0x00100000
1694 #define FSL_CORENET_DEVDISR_DDR2 0x00080000
1695 #define FSL_CORENET_DEVDISR_DBG 0x00010000
1696 #define FSL_CORENET_DEVDISR_NAL 0x00008000
1697 #define FSL_CORENET_DEVDISR_SATA1 0x00004000
1698 #define FSL_CORENET_DEVDISR_SATA2 0x00002000
1699 #define FSL_CORENET_DEVDISR_ELBC 0x00001000
1700 #define FSL_CORENET_DEVDISR_USB1 0x00000800
1701 #define FSL_CORENET_DEVDISR_USB2 0x00000400
1702 #define FSL_CORENET_DEVDISR_ESDHC 0x00000100
1703 #define FSL_CORENET_DEVDISR_GPIO 0x00000080
1704 #define FSL_CORENET_DEVDISR_ESPI 0x00000040
1705 #define FSL_CORENET_DEVDISR_I2C1 0x00000020
1706 #define FSL_CORENET_DEVDISR_I2C2 0x00000010
1707 #define FSL_CORENET_DEVDISR_DUART1 0x00000002
1708 #define FSL_CORENET_DEVDISR_DUART2 0x00000001
1709 #define FSL_CORENET_DEVDISR2_PME 0x80000000
1710 #define FSL_CORENET_DEVDISR2_SEC 0x40000000
1711 #define FSL_CORENET_DEVDISR2_QMBM 0x08000000
1712 #define FSL_CORENET_DEVDISR2_FM1 0x02000000
1713 #define FSL_CORENET_DEVDISR2_10GEC1 0x01000000
1714 #define FSL_CORENET_DEVDISR2_DTSEC1_1 0x00800000
1715 #define FSL_CORENET_DEVDISR2_DTSEC1_2 0x00400000
1716 #define FSL_CORENET_DEVDISR2_DTSEC1_3 0x00200000
1717 #define FSL_CORENET_DEVDISR2_DTSEC1_4 0x00100000
1718 #define FSL_CORENET_DEVDISR2_DTSEC1_5 0x00080000
1719 #define FSL_CORENET_DEVDISR2_FM2 0x00020000
1720 #define FSL_CORENET_DEVDISR2_10GEC2 0x00010000
1721 #define FSL_CORENET_DEVDISR2_DTSEC2_1 0x00008000
1722 #define FSL_CORENET_DEVDISR2_DTSEC2_2 0x00004000
1723 #define FSL_CORENET_DEVDISR2_DTSEC2_3 0x00002000
1724 #define FSL_CORENET_DEVDISR2_DTSEC2_4 0x00001000
1725 #define FSL_CORENET_DEVDISR2_DTSEC2_5 0x00000800
1741 #define FSL_CORENET_RSTRQMR1_SRDS_RST_MSK 0x00000800
1755 #define RCW_SB_EN_MASK 0x00200000
1761 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK 0x3f
1763 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xfc000000
1765 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00fe0000
1767 #define FSL_CORENET2_RCWSR4_SRDS3_PRTCL 0x0000f800
1769 #define FSL_CORENET2_RCWSR4_SRDS4_PRTCL 0x000000f8
1771 #define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000
1773 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xfe000000
1775 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00ff0000
1777 #define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000
1779 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff000000
1781 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00fe0000
1783 #define FSL_CORENET_RCWSR13_EC1 0x30000000 /* bits 418..419 */
1784 #define FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_RGMII 0x00000000
1785 #define FSL_CORENET_RCWSR13_EC1_FM1_GPIO 0x10000000
1786 #define FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_MII 0x20000000
1787 #define FSL_CORENET_RCWSR13_EC2 0x0c000000 /* bits 420..421 */
1788 #define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII 0x00000000
1789 #define FSL_CORENET_RCWSR13_EC2_FM1_GPIO 0x10000000
1790 #define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_MII 0x20000000
1791 #define FSL_CORENET_RCWSR13_MAC2_GMII_SEL 0x00000080
1792 #define FSL_CORENET_RCWSR13_MAC2_GMII_SEL_L2_SWITCH 0x00000000
1793 #define FSL_CORENET_RCWSR13_MAC2_GMII_SEL_ENET_PORT 0x80000000
1794 #define CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET 0x28
1795 #define PXCKEN_MASK 0x80000000
1796 #define PXCK_MASK 0x00FF0000
1799 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff800000
1801 #define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000
1802 #define FSL_CORENET_RCWSR13_EC1 0x30000000 /* bits 418..419 */
1803 #define FSL_CORENET_RCWSR13_EC1_RGMII 0x00000000
1804 #define FSL_CORENET_RCWSR13_EC1_GPIO 0x10000000
1805 #define FSL_CORENET_RCWSR13_EC2 0x0c000000
1806 #define FSL_CORENET_RCWSR13_EC2_RGMII 0x08000000
1807 #define CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET 0x28
1808 #define CONFIG_SYS_FSL_SCFG_IODSECR1_OFFSET 0xd00
1809 #define PXCKEN_MASK 0x80000000
1810 #define PXCK_MASK 0x00FF0000
1813 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff000000
1815 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00ff0000
1817 #define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000
1819 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S1_PLL1 0x00800000
1820 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S1_PLL2 0x00400000
1821 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S2_PLL1 0x00200000
1822 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S2_PLL2 0x00100000
1823 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S3_PLL1 0x00080000
1824 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S3_PLL2 0x00040000
1825 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S4_PLL1 0x00020000
1826 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S4_PLL2 0x00010000
1828 #define FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_MASK 0x00000011
1833 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK 0x1f
1834 #define FSL_CORENET_RCWSR4_SRDS_PRTCL 0xfc000000
1835 #define FSL_CORENET_RCWSR5_DDR_SYNC 0x00000080
1837 #define FSL_CORENET_RCWSR5_SRDS_EN 0x00002000
1838 #define FSL_CORENET_RCWSR5_SRDS2_EN 0x00001000
1839 #define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000
1840 #define FSL_CORENET_RCWSRn_SRDS_LPD_B2 0x3c000000 /* bits 162..165 */
1841 #define FSL_CORENET_RCWSRn_SRDS_LPD_B3 0x003c0000 /* bits 170..173 */
1844 #define FSL_CORENET_RCWSR7_MCK_TO_PLAT_RAT 0x00400000
1845 #define FSL_CORENET_RCWSR8_HOST_AGT_B1 0x00e00000
1846 #define FSL_CORENET_RCWSR8_HOST_AGT_B2 0x00100000
1847 #define FSL_CORENET_RCWSR11_EC1 0x00c00000 /* bits 360..361 */
1849 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC1 0x00000000
1850 #define FSL_CORENET_RCWSR11_EC1_FM1_USB1 0x00800000
1851 #define FSL_CORENET_RCWSR11_EC2 0x001c0000 /* bits 363..365 */
1852 #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC1 0x00000000
1853 #define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2 0x00080000
1854 #define FSL_CORENET_RCWSR11_EC2_USB2 0x00100000
1858 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_RGMII 0x00000000
1859 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_MII 0x00800000
1860 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_NONE 0x00c00000
1861 #define FSL_CORENET_RCWSR11_EC2 0x00180000 /* bits 363..364 */
1862 #define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_RGMII 0x00000000
1863 #define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_MII 0x00100000
1864 #define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_NONE 0x00180000
1867 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_RGMII 0x00000000
1868 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_MII 0x00800000
1869 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_NONE 0x00c00000
1870 #define FSL_CORENET_RCWSR11_EC2 0x00180000 /* bits 363..364 */
1871 #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_RGMII 0x00000000
1872 #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_MII 0x00100000
1873 #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_NONE 0x00180000
1876 #define FSL_CORENET_RCWSR13_EC1 0x60000000 /* bits 417..418 */
1877 #define FSL_CORENET_RCWSR13_EC1_FM2_DTSEC5_RGMII 0x00000000
1878 #define FSL_CORENET_RCWSR13_EC1_FM2_GPIO 0x40000000
1879 #define FSL_CORENET_RCWSR13_EC2 0x18000000 /* bits 419..420 */
1880 #define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII 0x00000000
1881 #define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC6_RGMII 0x08000000
1882 #define FSL_CORENET_RCWSR13_EC2_FM1_GPIO 0x10000000
1885 #define FSL_CORENET_RCWSR13_EC1 0x60000000 /* bits 417..418 */
1886 #define FSL_CORENET_RCWSR13_EC1_DTSEC3_RGMII 0x00000000
1887 #define FSL_CORENET_RCWSR13_EC1_GPIO 0x40000000
1888 #define FSL_CORENET_RCWSR13_EC2 0x18000000 /* bits 419..420 */
1889 #define FSL_CORENET_RCWSR13_EC2_DTSEC4_RGMII 0x00000000
1890 #define FSL_CORENET_RCWSR13_EC2_DTSEC10_RGMII 0x08000000
1891 #define FSL_CORENET_RCWSR13_EC2_GPIO 0x10000000
1969 #define TP_ITYP_AV 0x00000001 /* Initiator available */
1970 #define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1) /* Initiator Type */
1971 #define TP_ITYP_TYPE_OTHER 0x0
1972 #define TP_ITYP_TYPE_PPC 0x1 /* PowerPC */
1973 #define TP_ITYP_TYPE_SC 0x2 /* StarCore DSP */
1974 #define TP_ITYP_TYPE_HA 0x3 /* HW Accelerator */
1975 #define TP_ITYP_THDS(x) (((x) & 0x18) >> 3) /* # threads */
1976 #define TP_ITYP_VER(x) (((x) & 0xe0) >> 5) /* Initiator Version */
1978 #define TP_CLUSTER_EOC 0x80000000 /* end of clusters */
1979 #define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */
1982 #define FSL_CORENET_DCSR_SZ_MASK 0x00000003
1983 #define FSL_CORENET_DCSR_SZ_4M 0x0
1984 #define FSL_CORENET_DCSR_SZ_1G 0x3
1995 u8 res_004[0x0c];
1997 u8 res_014[0x0c];
1999 u8 res_100[0x680]; /* 0x100 */
2002 u8 res10[0x1c];
2004 u8 res21[0x280];
2005 u32 pllpgsr; /* 0xc00 Platform PLL General Status */
2006 u8 res16[0x1c];
2007 u32 plldgsr; /* 0xc20 DDR PLL General Status */
2008 u8 res17[0x3dc];
2096 u32 ippdexpcr0; /* IP Powerdown Exception Control 0 */
2112 u8 res18[0xf68];
2120 #define MPC85xx_PORPLLSR_DDR_RATIO 0x3e000000
2123 #define MPC85xx_PORPLLSR_DDR_RATIO 0x00003f00
2129 #define MPC85xx_PORPLLSR_DDR_RATIO 0x00003f00
2131 #define MPC85xx_PORPLLSR_DDR_RATIO 0x00003e00
2135 #define MPC85xx_PORPLLSR_QE_RATIO 0x3e000000
2137 #define MPC85xx_PORPLLSR_PLAT_RATIO 0x0000003e
2140 #define MPC85xx_PORBMSR_HA 0x00070000
2143 #define PORBMSR_ROMLOC_SPI 0x6
2144 #define PORBMSR_ROMLOC_SDHC 0x7
2145 #define PORBMSR_ROMLOC_NAND_2K 0x9
2146 #define PORBMSR_ROMLOC_NOR 0xf
2150 #define MPC85xx_PORDEVSR_SGMII1_DIS 0x10000000
2151 #define MPC85xx_PORDEVSR_SGMII2_DIS 0x08000000
2152 #define MPC85xx_PORDEVSR_TSEC1_PRTC 0x02000000
2154 #define MPC85xx_PORDEVSR_SGMII1_DIS 0x20000000
2155 #define MPC85xx_PORDEVSR_SGMII2_DIS 0x10000000
2157 #define MPC85xx_PORDEVSR_SGMII3_DIS 0x08000000
2158 #define MPC85xx_PORDEVSR_SGMII4_DIS 0x04000000
2159 #define MPC85xx_PORDEVSR_SRDS2_IO_SEL 0x38000000
2160 #define MPC85xx_PORDEVSR_PCI1 0x00800000
2162 #define MPC85xx_PORDEVSR_IO_SEL 0x007c0000
2165 #define MPC85xx_PORDEVSR_IO_SEL 0x00600000
2169 #define MPC85xx_PORDEVSR_IO_SEL 0x00600000
2172 #define MPC85xx_PORDEVSR_IO_SEL 0x00FE0000
2175 #define MPC85xx_PORDEVSR_IO_SEL 0x00e00000
2178 #define MPC85xx_PORDEVSR_IO_SEL 0x00780000
2182 #define MPC85xx_PORDEVSR_PCI2_ARB 0x00040000
2183 #define MPC85xx_PORDEVSR_PCI1_ARB 0x00020000
2184 #define MPC85xx_PORDEVSR_PCI1_PCI32 0x00010000
2185 #define MPC85xx_PORDEVSR_PCI1_SPD 0x00008000
2186 #define MPC85xx_PORDEVSR_PCI2_SPD 0x00004000
2187 #define MPC85xx_PORDEVSR_DRAM_RTYPE 0x00000060
2188 #define MPC85xx_PORDEVSR_RIO_CTLS 0x00000008
2189 #define MPC85xx_PORDEVSR_RIO_DEV_ID 0x00000007
2193 #define MPC85xx_PORDEVSR2_DDR_SPD_0 0x00000008
2196 #define MPC85xx_PORDEVSR2_SBC_MASK 0x10000000
2198 #define MPC85xx_PORDEVSR2_SEC_CFG 0x00000080
2204 #define MPC85xx_GENCFGR_SDHC_WP_INV 0x20000000
2222 #define MPC85xx_PMUXCR_TSEC1_0_1588 0x40000000
2223 #define MPC85xx_PMUXCR_TSEC1_0_RES 0xC0000000
2224 #define MPC85xx_PMUXCR_TSEC1_1_1588_TRIG 0x10000000
2225 #define MPC85xx_PMUXCR_TSEC1_1_GPIO_12 0x20000000
2226 #define MPC85xx_PMUXCR_TSEC1_1_RES 0x30000000
2227 #define MPC85xx_PMUXCR_TSEC1_2_DMA 0x04000000
2228 #define MPC85xx_PMUXCR_TSEC1_2_GPIO 0x08000000
2229 #define MPC85xx_PMUXCR_TSEC1_2_RES 0x0C000000
2230 #define MPC85xx_PMUXCR_TSEC1_3_RES 0x01000000
2231 #define MPC85xx_PMUXCR_TSEC1_3_GPIO_15 0x02000000
2232 #define MPC85xx_PMUXCR_IFC_ADDR16_SDHC 0x00400000
2233 #define MPC85xx_PMUXCR_IFC_ADDR16_USB 0x00800000
2234 #define MPC85xx_PMUXCR_IFC_ADDR16_IFC_CS2 0x00C00000
2235 #define MPC85xx_PMUXCR_IFC_ADDR17_18_SDHC 0x00100000
2236 #define MPC85xx_PMUXCR_IFC_ADDR17_18_USB 0x00200000
2237 #define MPC85xx_PMUXCR_IFC_ADDR17_18_DMA 0x00300000
2238 #define MPC85xx_PMUXCR_IFC_ADDR19_SDHC_DATA 0x00040000
2239 #define MPC85xx_PMUXCR_IFC_ADDR19_USB 0x00080000
2240 #define MPC85xx_PMUXCR_IFC_ADDR19_DMA 0x000C0000
2241 #define MPC85xx_PMUXCR_IFC_ADDR20_21_SDHC_DATA 0x00010000
2242 #define MPC85xx_PMUXCR_IFC_ADDR20_21_USB 0x00020000
2243 #define MPC85xx_PMUXCR_IFC_ADDR20_21_RES 0x00030000
2244 #define MPC85xx_PMUXCR_IFC_ADDR22_SDHC 0x00004000
2245 #define MPC85xx_PMUXCR_IFC_ADDR22_USB 0x00008000
2246 #define MPC85xx_PMUXCR_IFC_ADDR22_RES 0x0000C000
2247 #define MPC85xx_PMUXCR_IFC_ADDR23_SDHC 0x00001000
2248 #define MPC85xx_PMUXCR_IFC_ADDR23_USB 0x00002000
2249 #define MPC85xx_PMUXCR_IFC_ADDR23_RES 0x00003000
2250 #define MPC85xx_PMUXCR_IFC_ADDR24_SDHC 0x00000400
2251 #define MPC85xx_PMUXCR_IFC_ADDR24_USB 0x00000800
2252 #define MPC85xx_PMUXCR_IFC_ADDR24_RES 0x00000C00
2253 #define MPC85xx_PMUXCR_IFC_PAR_PERR_RES 0x00000300
2254 #define MPC85xx_PMUXCR_IFC_PAR_PERR_USB 0x00000200
2255 #define MPC85xx_PMUXCR_LCLK_RES 0x00000040
2256 #define MPC85xx_PMUXCR_LCLK_USB 0x00000080
2257 #define MPC85xx_PMUXCR_LCLK_IFC_CS3 0x000000C0
2258 #define MPC85xx_PMUXCR_SPI_RES 0x00000030
2259 #define MPC85xx_PMUXCR_SPI_GPIO 0x00000020
2260 #define MPC85xx_PMUXCR_CAN1_UART 0x00000004
2261 #define MPC85xx_PMUXCR_CAN1_TDM 0x00000008
2262 #define MPC85xx_PMUXCR_CAN1_RES 0x0000000C
2263 #define MPC85xx_PMUXCR_CAN2_UART 0x00000001
2264 #define MPC85xx_PMUXCR_CAN2_TDM 0x00000002
2265 #define MPC85xx_PMUXCR_CAN2_RES 0x00000003
2268 #define MPC85xx_PMUXCR_TSEC1_1 0x10000000
2270 #define MPC85xx_PMUXCR_SD_DATA 0x80000000
2271 #define MPC85xx_PMUXCR_SDHC_CD 0x40000000
2272 #define MPC85xx_PMUXCR_SDHC_WP 0x20000000
2273 #define MPC85xx_PMUXCR_ELBC_OFF_USB2_ON 0x01000000
2274 #define MPC85xx_PMUXCR_TDM_ENA 0x00800000
2275 #define MPC85xx_PMUXCR_QE0 0x00008000
2276 #define MPC85xx_PMUXCR_QE1 0x00004000
2277 #define MPC85xx_PMUXCR_QE2 0x00002000
2278 #define MPC85xx_PMUXCR_QE3 0x00001000
2279 #define MPC85xx_PMUXCR_QE4 0x00000800
2280 #define MPC85xx_PMUXCR_QE5 0x00000400
2281 #define MPC85xx_PMUXCR_QE6 0x00000200
2282 #define MPC85xx_PMUXCR_QE7 0x00000100
2283 #define MPC85xx_PMUXCR_QE8 0x00000080
2284 #define MPC85xx_PMUXCR_QE9 0x00000040
2285 #define MPC85xx_PMUXCR_QE10 0x00000020
2286 #define MPC85xx_PMUXCR_QE11 0x00000010
2287 #define MPC85xx_PMUXCR_QE12 0x00000008
2290 #define MPC85xx_PMUXCR_TDM_MASK 0x0001cc00
2291 #define MPC85xx_PMUXCR_TDM 0x00014800
2292 #define MPC85xx_PMUXCR_SPI_MASK 0x00600000
2293 #define MPC85xx_PMUXCR_SPI 0x00000000
2296 #define MPC85xx_PMUXCR_TSEC2_DMA_GPIO_IRQ 0x40000000
2297 #define MPC85xx_PMUXCR_TSEC2_USB 0xC0000000
2298 #define MPC85xx_PMUXCR_TSEC2_1588_PPS 0x10000000
2299 #define MPC85xx_PMUXCR_TSEC2_1588_RSVD 0x30000000
2300 #define MPC85xx_PMUXCR_IFC_AD_GPIO 0x04000000
2301 #define MPC85xx_PMUXCR_IFC_AD_GPIO_MASK 0x0C000000
2302 #define MPC85xx_PMUXCR_IFC_AD15_GPIO 0x01000000
2303 #define MPC85xx_PMUXCR_IFC_AD15_TIMER2 0x02000000
2304 #define MPC85xx_PMUXCR_IFC_AD16_GPO8 0x00400000
2305 #define MPC85xx_PMUXCR_IFC_AD16_MSRCID0 0x00800000
2306 #define MPC85xx_PMUXCR_IFC_AD17_GPO 0x00100000
2307 #define MPC85xx_PMUXCR_IFC_AD17_GPO_MASK 0x00300000
2308 #define MPC85xx_PMUXCR_IFC_AD17_MSRCID_DSP 0x00200000
2309 #define MPC85xx_PMUXCR_IFC_CS2_GPO65 0x00040000
2310 #define MPC85xx_PMUXCR_IFC_CS2_DSP_TDI 0x00080000
2311 #define MPC85xx_PMUXCR_SDHC_USIM 0x00010000
2312 #define MPC85xx_PMUXCR_SDHC_TDM_RFS_RCK 0x00020000
2313 #define MPC85xx_PMUXCR_SDHC_GPIO77 0x00030000
2314 #define MPC85xx_PMUXCR_SDHC_RESV 0x00004000
2315 #define MPC85xx_PMUXCR_SDHC_TDM_TXD_RXD 0x00008000
2316 #define MPC85xx_PMUXCR_SDHC_GPIO_TIMER4 0x0000C000
2317 #define MPC85xx_PMUXCR_USB_CLK_UART_SIN 0x00001000
2318 #define MPC85xx_PMUXCR_USB_CLK_GPIO69 0x00002000
2319 #define MPC85xx_PMUXCR_USB_CLK_TIMER3 0x00003000
2320 #define MPC85xx_PMUXCR_USB_UART_GPIO0 0x00000400
2321 #define MPC85xx_PMUXCR_USB_RSVD 0x00000C00
2322 #define MPC85xx_PMUXCR_USB_GPIO62_TRIG_IN 0x00000800
2323 #define MPC85xx_PMUXCR_USB_D1_2_IIC2_SDA_SCL 0x00000100
2324 #define MPC85xx_PMUXCR_USB_D1_2_GPIO71_72 0x00000200
2325 #define MPC85xx_PMUXCR_USB_D1_2_RSVD 0x00000300
2326 #define MPC85xx_PMUXCR_USB_DIR_GPIO2 0x00000040
2327 #define MPC85xx_PMUXCR_USB_DIR_TIMER1 0x00000080
2328 #define MPC85xx_PMUXCR_USB_DIR_MCP_B 0x000000C0
2329 #define MPC85xx_PMUXCR_SPI1_UART3 0x00000010
2330 #define MPC85xx_PMUXCR_SPI1_SIM 0x00000020
2331 #define MPC85xx_PMUXCR_SPI1_CKSTP_IN_GPO74 0x00000030
2332 #define MPC85xx_PMUXCR_SPI1_CS2_CKSTP_OUT_B 0x00000004
2333 #define MPC85xx_PMUXCR_SPI1_CS2_dbg_adi1_rxen 0x00000008
2334 #define MPC85xx_PMUXCR_SPI1_CS2_GPO75 0x0000000C
2335 #define MPC85xx_PMUXCR_SPI1_CS3_ANT_TCXO_PWM 0x00000001
2336 #define MPC85xx_PMUXCR_SPI1_CS3_dbg_adi2_rxen 0x00000002
2337 #define MPC85xx_PMUXCR_SPI1_CS3_GPO76 0x00000003
2340 #define MPC85xx_PMUXCR0_SIM_SEL_MASK 0x0003b000
2341 #define MPC85xx_PMUXCR0_SIM_SEL 0x00014000
2344 #define MPC85xx_PMUXCR_SPI_MASK 0x00000300
2345 #define MPC85xx_PMUXCR_SPI 0x00000000
2346 #define MPC85xx_PMUXCR_SPI_GPIO 0x00000100
2350 #define MPC85xx_PMUXCR2_UART_GPIO 0x40000000
2351 #define MPC85xx_PMUXCR2_UART_TDM 0x80000000
2352 #define MPC85xx_PMUXCR2_UART_RES 0xC0000000
2353 #define MPC85xx_PMUXCR2_IRQ2_TRIG_IN 0x10000000
2354 #define MPC85xx_PMUXCR2_IRQ2_RES 0x30000000
2355 #define MPC85xx_PMUXCR2_IRQ3_SRESET 0x04000000
2356 #define MPC85xx_PMUXCR2_IRQ3_RES 0x0C000000
2357 #define MPC85xx_PMUXCR2_GPIO01_DRVVBUS 0x01000000
2358 #define MPC85xx_PMUXCR2_GPIO01_RES 0x03000000
2359 #define MPC85xx_PMUXCR2_GPIO23_CKSTP 0x00400000
2360 #define MPC85xx_PMUXCR2_GPIO23_RES 0x00800000
2361 #define MPC85xx_PMUXCR2_GPIO23_USB 0x00C00000
2362 #define MPC85xx_PMUXCR2_GPIO4_MCP 0x00100000
2363 #define MPC85xx_PMUXCR2_GPIO4_RES 0x00200000
2364 #define MPC85xx_PMUXCR2_GPIO4_CLK_OUT 0x00300000
2365 #define MPC85xx_PMUXCR2_GPIO5_UDE 0x00040000
2366 #define MPC85xx_PMUXCR2_GPIO5_RES 0x00080000
2367 #define MPC85xx_PMUXCR2_READY_ASLEEP 0x00020000
2368 #define MPC85xx_PMUXCR2_DDR_ECC_MUX 0x00010000
2369 #define MPC85xx_PMUXCR2_DEBUG_PORT_EXPOSE 0x00008000
2370 #define MPC85xx_PMUXCR2_POST_EXPOSE 0x00004000
2371 #define MPC85xx_PMUXCR2_DEBUG_MUX_SEL_USBPHY 0x00002000
2372 #define MPC85xx_PMUXCR2_PLL_LKDT_EXPOSE 0x00001000
2375 #define MPC85xx_PMUXCR2_ETSECUSB_MASK 0x001f8000
2376 #define MPC85xx_PMUXCR2_USB 0x00150000
2380 #define MPC85xx_PMUXCR2_UART_CTS_B0_SIM_PD 0X40000000
2381 #define MPC85xx_PMUXCR2_UART_CTS_B0_DSP_TMS 0X80000000
2382 #define MPC85xx_PMUXCR2_UART_CTS_B0_GPIO42 0xC0000000
2383 #define MPC85xx_PMUXCR2_UART_RTS_B0_PWM2 0x10000000
2384 #define MPC85xx_PMUXCR2_UART_RTS_B0_DSP_TCK 0x20000000
2385 #define MPC85xx_PMUXCR2_UART_RTS_B0_GPIO43 0x30000000
2386 #define MPC85xx_PMUXCR2_UART_CTS_B1_SIM_PD 0x04000000
2387 #define MPC85xx_PMUXCR2_UART_CTS_B1_SRESET_B 0x08000000
2388 #define MPC85xx_PMUXCR2_UART_CTS_B1_GPIO44 0x0C000000
2389 #define MPC85xx_PMUXCR2_UART_RTS_B1_PPS_LED 0x01000000
2390 #define MPC85xx_PMUXCR2_UART_RTS_B1_RSVD 0x02000000
2391 #define MPC85xx_PMUXCR2_UART_RTS_B1_GPIO45 0x03000000
2392 #define MPC85xx_PMUXCR2_TRIG_OUT_ASLEEP 0x00400000
2393 #define MPC85xx_PMUXCR2_TRIG_OUT_DSP_TRST_B 0x00800000
2394 #define MPC85xx_PMUXCR2_ANT1_TIMER5 0x00100000
2395 #define MPC85xx_PMUXCR2_ANT1_TSEC_1588 0x00200000
2396 #define MPC85xx_PMUXCR2_ANT1_GPIO95_19 0x00300000
2397 #define MPC85xx_PMUXCR2_ANT1_TX_RX_FRAME_MAX3_LOCK 0x00040000
2398 #define MPC85xx_PMUXCR2_ANT1_TX_RX_FRAME_RSVD 0x00080000
2399 #define MPC85xx_PMUXCR2_ANT1_TX_RX_FRAME_GPIO80_20 0x000C0000
2400 #define MPC85xx_PMUXCR2_ANT1_DIO0_3_SPI3_CS0 0x00010000
2401 #define MPC85xx_PMUXCR2_ANT1_DIO0_3_ANT2_DO_3 0x00020000
2402 #define MPC85xx_PMUXCR2_ANT1_DIO0_3_GPIO81_84 0x00030000
2403 #define MPC85xx_PMUXCR2_ANT1_DIO4_7_SPI4 0x00004000
2404 #define MPC85xx_PMUXCR2_ANT1_DIO4_7_ANT2_DO4_7 0x00008000
2405 #define MPC85xx_PMUXCR2_ANT1_DIO4_7_GPIO85_88 0x0000C000
2406 #define MPC85xx_PMUXCR2_ANT1_DIO8_9_MAX2_1_LOCK 0x00001000
2407 #define MPC85xx_PMUXCR2_ANT1_DIO8_9_ANT2_DO8_9 0x00002000
2408 #define MPC85xx_PMUXCR2_ANT1_DIO8_9_GPIO21_22 0x00003000
2409 #define MPC85xx_PMUXCR2_ANT1_DIO10_11_TIMER6_7 0x00000400
2410 #define MPC85xx_PMUXCR2_ANT1_DIO10_11_ANT2_DO10_11 0x00000800
2411 #define MPC85xx_PMUXCR2_ANT1_DIO10_11_GPIO23_24 0x00000C00
2412 #define MPC85xx_PMUXCR2_ANT2_RSVD 0x00000100
2413 #define MPC85xx_PMUXCR2_ANT2_GPO90_91_DMA 0x00000300
2414 #define MPC85xx_PMUXCR2_ANT2_ENABLE_DIO0_10_USB 0x00000040
2415 #define MPC85xx_PMUXCR2_ANT2_ENABLE_DIO0_10_GPIO 0x000000C0
2416 #define MPC85xx_PMUXCR2_ANT2_DIO11_RSVD 0x00000010
2417 #define MPC85xx_PMUXCR2_ANT2_DIO11_TIMER8 0x00000020
2418 #define MPC85xx_PMUXCR2_ANT2_DIO11_GPIO61 0x00000030
2419 #define MPC85xx_PMUXCR2_ANT3_AGC_GPO53 0x00000004
2420 #define MPC85xx_PMUXCR2_ANT3_DO_TDM 0x00000001
2421 #define MPC85xx_PMUXCR2_ANT3_DO_GPIO46_49 0x00000002
2425 #define MPC85xx_PMUXCR3_ANT3_DO4_5_TDM 0x40000000
2426 #define MPC85xx_PMUXCR3_ANT3_DO4_5_GPIO_50_51 0x80000000
2427 #define MPC85xx_PMUXCR3_ANT3_DO6_7_TRIG_IN_SRESET_B 0x10000000
2428 #define MPC85xx_PMUXCR3_ANT3_DO6_7_GPIO_52_53 0x20000000
2429 #define MPC85xx_PMUXCR3_ANT3_DO8_MCP_B 0x04000000
2430 #define MPC85xx_PMUXCR3_ANT3_DO8_GPIO54 0x08000000
2431 #define MPC85xx_PMUXCR3_ANT3_DO9_10_CKSTP_IN_OUT 0x01000000
2432 #define MPC85xx_PMUXCR3_ANT3_DO9_10_GPIO55_56 0x02000000
2433 #define MPC85xx_PMUXCR3_ANT3_DO11_IRQ_OUT 0x00400000
2434 #define MPC85xx_PMUXCR3_ANT3_DO11_GPIO57 0x00800000
2435 #define MPC85xx_PMUXCR3_SPI2_CS2_GPO93 0x00100000
2436 #define MPC85xx_PMUXCR3_SPI2_CS3_GPO94 0x00040000
2437 #define MPC85xx_PMUXCR3_ANT2_AGC_RSVD 0x00010000
2438 #define MPC85xx_PMUXCR3_ANT2_GPO89 0x00030000
2441 #define MPC85xx_PMUXCR3_USB_SEL_MASK 0x0000ff00
2442 #define MPC85xx_PMUXCR3_UART2_SEL 0x00005000
2443 #define MPC85xx_PMUXCR3_UART3_SEL_MASK 0xc0000000
2444 #define MPC85xx_PMUXCR3_UART3_SEL 0x40000000
2451 #define MPC85xx_DEVDISR_PCI1 0x80000000
2452 #define MPC85xx_DEVDISR_PCI2 0x40000000
2453 #define MPC85xx_DEVDISR_PCIE 0x20000000
2454 #define MPC85xx_DEVDISR_LBC 0x08000000
2455 #define MPC85xx_DEVDISR_PCIE2 0x04000000
2456 #define MPC85xx_DEVDISR_PCIE3 0x02000000
2457 #define MPC85xx_DEVDISR_SEC 0x01000000
2458 #define MPC85xx_DEVDISR_SRIO 0x00080000
2459 #define MPC85xx_DEVDISR_RMSG 0x00040000
2460 #define MPC85xx_DEVDISR_DDR 0x00010000
2461 #define MPC85xx_DEVDISR_CPU 0x00008000
2463 #define MPC85xx_DEVDISR_TB 0x00004000
2465 #define MPC85xx_DEVDISR_CPU1 0x00002000
2466 #define MPC85xx_DEVDISR_TB1 0x00001000
2467 #define MPC85xx_DEVDISR_DMA 0x00000400
2468 #define MPC85xx_DEVDISR_TSEC1 0x00000080
2469 #define MPC85xx_DEVDISR_TSEC2 0x00000040
2470 #define MPC85xx_DEVDISR_TSEC3 0x00000020
2471 #define MPC85xx_DEVDISR_TSEC4 0x00000010
2472 #define MPC85xx_DEVDISR_I2C 0x00000004
2473 #define MPC85xx_DEVDISR_DUART 0x00000002
2506 #define HALTED_TO_HALT_REQ_MASK_0 0x80000000
2511 u32 lbiuiplldcr0; /* LBIU PLL Debug Reg 0 */
2522 #define SDHCDCR_CD_INV 0x80000000 /* invert SDHC card detect */
2535 #define SRDS_RSTCTL_RST 0x80000000
2536 #define SRDS_RSTCTL_RSTDONE 0x40000000
2537 #define SRDS_RSTCTL_RSTERR 0x20000000
2538 #define SRDS_RSTCTL_SWRST 0x10000000
2539 #define SRDS_RSTCTL_SDEN 0x00000020
2540 #define SRDS_RSTCTL_SDRST_B 0x00000040
2541 #define SRDS_RSTCTL_PLLRST_B 0x00000080
2543 u32 pllcr0; /* PLL Control Register 0 */
2544 #define SRDS_PLLCR0_POFF 0x80000000
2545 #define SRDS_PLLCR0_RFCK_SEL_MASK 0x70000000
2546 #define SRDS_PLLCR0_RFCK_SEL_100 0x00000000
2547 #define SRDS_PLLCR0_RFCK_SEL_125 0x10000000
2548 #define SRDS_PLLCR0_RFCK_SEL_156_25 0x20000000
2549 #define SRDS_PLLCR0_RFCK_SEL_150 0x30000000
2550 #define SRDS_PLLCR0_RFCK_SEL_161_13 0x40000000
2551 #define SRDS_PLLCR0_RFCK_SEL_122_88 0x50000000
2552 #define SRDS_PLLCR0_PLL_LCK 0x00800000
2553 #define SRDS_PLLCR0_DCBIAS_OUT_EN 0x02000000
2554 #define SRDS_PLLCR0_FRATE_SEL_MASK 0x000f0000
2555 #define SRDS_PLLCR0_FRATE_SEL_5 0x00000000
2556 #define SRDS_PLLCR0_FRATE_SEL_4_9152 0x00030000
2557 #define SRDS_PLLCR0_FRATE_SEL_3_75 0x00050000
2558 #define SRDS_PLLCR0_FRATE_SEL_5_15 0x00060000
2559 #define SRDS_PLLCR0_FRATE_SEL_4 0x00070000
2560 #define SRDS_PLLCR0_FRATE_SEL_3_125 0x00090000
2561 #define SRDS_PLLCR0_FRATE_SEL_3_0 0x000a0000
2562 #define SRDS_PLLCR0_FRATE_SEL_3_072 0x000c0000
2563 #define SRDS_PLLCR0_DCBIAS_OVRD 0x000000F0
2566 #define SRDS_PLLCR1_BCAP_EN 0x20000000
2567 #define SRDS_PLLCR1_BCAP_OVD 0x10000000
2568 #define SRDS_PLLCR1_PLL_FCAP 0x001F8000
2570 #define SRDS_PLLCR1_PLL_BWSEL 0x08000000
2571 #define SRDS_PLLCR1_BYP_CAL 0x02000000
2572 u32 pllsr2; /* At 0x00c, PLL Status Register 2 */
2573 #define SRDS_PLLSR2_BCAP_EN 0x00800000
2575 #define SRDS_PLLSR2_FCAP 0x003F0000
2577 #define SRDS_PLLSR2_DCBIAS 0x000F0000
2581 u8 res_18[0x20-0x18];
2583 u8 res_40[0x90-0x40];
2584 u32 srdstcalcr; /* 0x90 TX Calibration Control */
2585 u8 res_94[0xa0-0x94];
2586 u32 srdsrcalcr; /* 0xa0 RX Calibration Control */
2587 u8 res_a4[0xb0-0xa4];
2588 u32 srdsgr0; /* 0xb0 General Register 0 */
2589 u8 res_b4[0xe0-0xb4];
2590 u32 srdspccr0; /* 0xe0 Protocol Converter Config 0 */
2591 u32 srdspccr1; /* 0xe4 Protocol Converter Config 1 */
2592 u32 srdspccr2; /* 0xe8 Protocol Converter Config 2 */
2593 u32 srdspccr3; /* 0xec Protocol Converter Config 3 */
2594 u32 srdspccr4; /* 0xf0 Protocol Converter Config 4 */
2595 u8 res_f4[0x100-0xf4];
2597 u32 lnpssr; /* 0x100, 0x120, ..., 0x1e0 */
2598 u8 res_104[0x120-0x104];
2600 u8 res_200[0x800-0x200];
2602 u32 gcr0; /* 0x800 General Control Register 0 */
2603 u32 gcr1; /* 0x804 General Control Register 1 */
2604 u32 gcr2; /* 0x808 General Control Register 2 */
2606 u32 recr0; /* 0x810 Receive Equalization Control */
2608 u32 tecr0; /* 0x818 Transmit Equalization Control */
2610 u32 ttlcr0; /* 0x820 Transition Tracking Loop Ctrl 0 */
2611 u8 res_824[0x840-0x824];
2613 u8 res_a00[0x1000-0xa00]; /* from 0xa00 to 0xfff */
2623 #define SRDS_RSTCTL_RST 0x80000000
2624 #define SRDS_RSTCTL_RSTDONE 0x40000000
2625 #define SRDS_RSTCTL_RSTERR 0x20000000
2626 #define SRDS_RSTCTL_SDPD 0x00000020
2627 u32 pllcr0; /* PLL Control Register 0 */
2628 #define SRDS_PLLCR0_RFCK_SEL_MASK 0x70000000
2629 #define SRDS_PLLCR0_PVCOCNT_EN 0x02000000
2630 #define SRDS_PLLCR0_RFCK_SEL_100 0x00000000
2631 #define SRDS_PLLCR0_RFCK_SEL_125 0x10000000
2632 #define SRDS_PLLCR0_RFCK_SEL_156_25 0x20000000
2633 #define SRDS_PLLCR0_RFCK_SEL_150 0x30000000
2634 #define SRDS_PLLCR0_RFCK_SEL_161_13 0x40000000
2635 #define SRDS_PLLCR0_FRATE_SEL_MASK 0x00030000
2636 #define SRDS_PLLCR0_FRATE_SEL_5 0x00000000
2637 #define SRDS_PLLCR0_FRATE_SEL_6_25 0x00010000
2639 #define SRDS_PLLCR1_PLL_BWSEL 0x08000000
2647 u32 srdsgr0; /* General Register 0 */
2649 u32 srdspccr0; /* Protocol Converter Config 0 */
2652 #define SRDS_PCCR2_RST_XGMII1 0x00800000
2653 #define SRDS_PCCR2_RST_XGMII2 0x00400000
2656 u32 gcr0; /* General Control Register 0 */
2657 #define SRDS_GCR0_RRST 0x00400000
2658 #define SRDS_GCR0_1STLANE 0x00010000
2659 #define SRDS_GCR0_UOTHL 0x00100000
2661 #define SRDS_GCR1_REIDL_CTL_MASK 0x001f0000
2662 #define SRDS_GCR1_REIDL_CTL_PCIE 0x00100000
2663 #define SRDS_GCR1_REIDL_CTL_SRIO 0x00000000
2664 #define SRDS_GCR1_REIDL_CTL_SGMII 0x00040000
2665 #define SRDS_GCR1_OPAD_CTL 0x04000000
2667 u32 tecr0; /* TX Equalization Control Reg 0 */
2668 #define SRDS_TECR0_TEQ_TYPE_MASK 0x30000000
2669 #define SRDS_TECR0_TEQ_TYPE_2LVL 0x10000000
2671 u32 ttlcr0; /* Transition Tracking Loop Ctrl 0 */
2672 #define SRDS_TTLCR0_FLT_SEL_MASK 0x3f000000
2673 #define SRDS_TTLCR0_FLT_SEL_KFR_26 0x10000000
2674 #define SRDS_TTLCR0_FLT_SEL_KPH_28 0x08000000
2675 #define SRDS_TTLCR0_FLT_SEL_750PPM 0x03000000
2676 #define SRDS_TTLCR0_PM_DIS 0x00004000
2677 #define SRDS_TTLCR0_FREQOVD_EN 0x00000001
2685 FSL_SRDS_B1_LANE_A = 0,
2707 u8 res0[0x200];
2710 u32 qcsp_lio_cfg; /* 0x0 - SW Portal n LIO cfg */
2711 u32 qcsp_io_cfg; /* 0x4 - SW Portal n IO cfg */
2713 u32 qcsp_dd_cfg; /* 0xc - SW Portal n Dynamic Debug cfg */
2717 u8 res[0xbf8 - 0x200];
2722 u8 res1[0x8];
2724 u8 res2[0xc];
2727 u8 res3[0x8];
2729 u8 res4[0x4c];
2732 u8 res5[0x78];
2739 u8 res7[0x2e8];
2742 u32 qcsp_lio_cfg; /* 0x0 - SW Portal n LIO cfg */
2743 u32 qcsp_io_cfg; /* 0x4 - SW Portal n IO cfg */
2745 u32 qcsp_dd_cfg; /* 0xc - SW Portal n Dynamic Debug cfg*/
2752 u8 res[0xbf8];
2757 u8 res1[0x8];
2759 u8 res2[0xf0];
2762 u8 res7[0x2f4];
2766 u8 res0[0x804];
2768 u8 res1[0x1f8];
2772 u8 res3[0x1e8];
2775 u8 res4[0x400];
2795 u8 res0[0x543];
2797 u8 res1[0xab8];
2800 u32 cfg0; /* cfg register 0 */
2802 u8 res1[0x3f8];
2804 u8 res[0x800];
2811 u8 res0[0xf64];
2815 u8 res4[0x1f090];
2821 u8 res_00[0x40];
2826 u8 res_50[0x50];
2829 u8 res_a8[0x8];
2831 u8 res_b4[0xc];
2838 u8 res_d8[0x8];
2841 u8 res_e8[0x8];
2843 u8 res_f4[0xf0c];
2848 #define CONFIG_SYS_FSL_CORENET_CCM_OFFSET 0x0000
2850 #define CONFIG_SYS_FSL_CORENET_PMAN1_OFFSET 0x4000
2851 #define CONFIG_SYS_FSL_CORENET_PMAN2_OFFSET 0x5000
2852 #define CONFIG_SYS_FSL_CORENET_PMAN3_OFFSET 0x6000
2854 #define CONFIG_SYS_MPC8xxx_DDR_OFFSET 0x8000
2855 #define CONFIG_SYS_MPC8xxx_DDR2_OFFSET 0x9000
2856 #define CONFIG_SYS_MPC8xxx_DDR3_OFFSET 0xA000
2857 #define CONFIG_SYS_FSL_CORENET_CLK_OFFSET 0xE1000
2858 #define CONFIG_SYS_FSL_CORENET_RCPM_OFFSET 0xE2000
2860 /* In SFPv3, OSPR register is now at offset 0x200.
2862 #define CONFIG_SYS_OSPR_OFFSET 0x200
2863 #define CONFIG_SYS_SFP_OFFSET (0xE8000 + CONFIG_SYS_OSPR_OFFSET)
2865 #define CONFIG_SYS_SFP_OFFSET 0xE8000
2867 #define CONFIG_SYS_FSL_CORENET_SERDES_OFFSET 0xEA000
2868 #define CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET 0xEB000
2869 #define CONFIG_SYS_FSL_CORENET_SERDES3_OFFSET 0xEC000
2870 #define CONFIG_SYS_FSL_CORENET_SERDES4_OFFSET 0xED000
2871 #define CONFIG_SYS_FSL_CPC_OFFSET 0x10000
2872 #define CONFIG_SYS_FSL_SCFG_OFFSET 0xFC000
2873 #define CONFIG_SYS_FSL_PAMU_OFFSET 0x20000
2874 #define CONFIG_SYS_MPC85xx_DMA1_OFFSET 0x100000
2875 #define CONFIG_SYS_MPC85xx_DMA2_OFFSET 0x101000
2876 #define CONFIG_SYS_MPC85xx_DMA3_OFFSET 0x102000
2878 #define CONFIG_SYS_MPC85xx_ESPI_OFFSET 0x110000
2879 #define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x114000
2880 #define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x124000
2881 #define CONFIG_SYS_MPC85xx_IFC_OFFSET 0x124000
2882 #define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0x130000
2883 #define CONFIG_SYS_MPC85xx_TDM_OFFSET 0x185000
2884 #define CONFIG_SYS_MPC85xx_QE_OFFSET 0x140000
2885 #define CONFIG_SYS_FSL_CORENET_RMAN_OFFSET 0x1e0000
2888 #define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0x240000
2889 #define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x250000
2890 #define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x260000
2891 #define CONFIG_SYS_MPC85xx_PCIE4_OFFSET 0x270000
2893 #define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0x200000
2894 #define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x201000
2895 #define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x202000
2896 #define CONFIG_SYS_MPC85xx_PCIE4_OFFSET 0x203000
2898 #define CONFIG_SYS_MPC85xx_USB1_OFFSET 0x210000
2899 #define CONFIG_SYS_MPC85xx_USB2_OFFSET 0x211000
2900 #define CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET 0x214000
2901 #define CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET 0x214100
2902 #define CONFIG_SYS_MPC85xx_SATA1_OFFSET 0x220000
2903 #define CONFIG_SYS_MPC85xx_SATA2_OFFSET 0x221000
2904 #define CONFIG_SYS_FSL_SEC_OFFSET 0x300000
2905 #define CONFIG_SYS_FSL_JR0_OFFSET 0x301000
2906 #define CONFIG_SYS_SEC_MON_OFFSET 0x314000
2907 #define CONFIG_SYS_FSL_CORENET_PME_OFFSET 0x316000
2908 #define CONFIG_SYS_FSL_QMAN_OFFSET 0x318000
2909 #define CONFIG_SYS_FSL_BMAN_OFFSET 0x31a000
2910 #define CONFIG_SYS_FSL_RAID_ENGINE_OFFSET 0x320000
2911 #define CONFIG_SYS_FSL_FM1_OFFSET 0x400000
2912 #define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0x488000
2913 #define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0x489000
2914 #define CONFIG_SYS_FSL_FM1_RX2_1G_OFFSET 0x48a000
2915 #define CONFIG_SYS_FSL_FM1_RX3_1G_OFFSET 0x48b000
2916 #define CONFIG_SYS_FSL_FM1_RX4_1G_OFFSET 0x48c000
2917 #define CONFIG_SYS_FSL_FM1_RX5_1G_OFFSET 0x48d000
2918 #define CONFIG_SYS_FSL_FM1_RX0_10G_OFFSET 0x490000
2919 #define CONFIG_SYS_FSL_FM1_RX1_10G_OFFSET 0x491000
2920 #define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0x4e0000
2921 #define CONFIG_SYS_FSL_FM2_OFFSET 0x500000
2922 #define CONFIG_SYS_FSL_FM2_RX0_1G_OFFSET 0x588000
2923 #define CONFIG_SYS_FSL_FM2_RX1_1G_OFFSET 0x589000
2924 #define CONFIG_SYS_FSL_FM2_RX2_1G_OFFSET 0x58a000
2925 #define CONFIG_SYS_FSL_FM2_RX3_1G_OFFSET 0x58b000
2926 #define CONFIG_SYS_FSL_FM2_RX4_1G_OFFSET 0x58c000
2927 #define CONFIG_SYS_FSL_FM2_RX5_1G_OFFSET 0x58d000
2928 #define CONFIG_SYS_FSL_FM2_RX0_10G_OFFSET 0x590000
2929 #define CONFIG_SYS_FSL_FM2_RX1_10G_OFFSET 0x591000
2930 #define CONFIG_SYS_FSL_CLUSTER_1_L2_OFFSET 0xC20000
2932 #define CONFIG_SYS_MPC85xx_ECM_OFFSET 0x0000
2933 #define CONFIG_SYS_MPC8xxx_DDR_OFFSET 0x2000
2934 #define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x5000
2935 #define CONFIG_SYS_MPC8xxx_DDR2_OFFSET 0x6000
2936 #define CONFIG_SYS_MPC85xx_ESPI_OFFSET 0x7000
2937 #define CONFIG_SYS_MPC85xx_PCI1_OFFSET 0x8000
2938 #define CONFIG_SYS_MPC85xx_PCIX_OFFSET 0x8000
2939 #define CONFIG_SYS_MPC85xx_PCI2_OFFSET 0x9000
2940 #define CONFIG_SYS_MPC85xx_PCIX2_OFFSET 0x9000
2941 #define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0xa000
2942 #define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x9000
2944 #define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x8000
2946 #define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0xb000
2948 #define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0xF000
2949 #define CONFIG_SYS_MPC85xx_SATA1_OFFSET 0x18000
2950 #define CONFIG_SYS_MPC85xx_SATA2_OFFSET 0x19000
2951 #define CONFIG_SYS_MPC85xx_IFC_OFFSET 0x1e000
2952 #define CONFIG_SYS_MPC85xx_L2_OFFSET 0x20000
2953 #define CONFIG_SYS_MPC85xx_DMA_OFFSET 0x21000
2954 #define CONFIG_SYS_MPC85xx_USB1_OFFSET 0x22000
2955 #define CONFIG_SYS_MPC85xx_USB2_OFFSET 0x23000
2956 #define CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET 0xE5000
2957 #define CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET 0xE5100
2959 #define CONFIG_SYS_TSEC1_OFFSET 0xB0000
2961 #define CONFIG_SYS_TSEC1_OFFSET 0x10000
2963 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
2965 #define CONFIG_SYS_MDIO1_OFFSET 0x24000
2966 #define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x2e000
2968 #define CONFIG_SYS_FSL_SEC_OFFSET 0x80000
2969 #define CONFIG_SYS_FSL_JR0_OFFSET 0x81000
2971 #define CONFIG_SYS_FSL_SEC_OFFSET 0x30000
2972 #define CONFIG_SYS_FSL_JR0_OFFSET 0x31000
2974 #define CONFIG_SYS_MPC85xx_SERDES2_OFFSET 0xE3100
2975 #define CONFIG_SYS_MPC85xx_SERDES1_OFFSET 0xE3000
2976 #define CONFIG_SYS_SEC_MON_OFFSET 0xE6000
2977 #define CONFIG_SYS_SFP_OFFSET 0xE7000
2978 #define CONFIG_SYS_MPC85xx_CPM_OFFSET 0x80000
2979 #define CONFIG_SYS_FSL_QMAN_OFFSET 0x88000
2980 #define CONFIG_SYS_FSL_BMAN_OFFSET 0x8a000
2981 #define CONFIG_SYS_FSL_FM1_OFFSET 0x100000
2982 #define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0x188000
2983 #define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0x189000
2984 #define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0x1e0000
2987 #define CONFIG_SYS_MPC85xx_PIC_OFFSET 0x40000
2988 #define CONFIG_SYS_MPC85xx_GUTS_OFFSET 0xE0000
2989 #define CONFIG_SYS_FSL_SRIO_OFFSET 0xC0000
2992 #define CONFIG_SYS_FSL_DSP_CCSR_DDR_OFFSET 0x10000
3116 u32 l2csr0; /* 0x000 L2 cache control and status register 0 */
3117 u32 l2csr1; /* 0x004 L2 cache control and status register 1 */
3118 u32 l2cfg0; /* 0x008 L2 cache configuration register 0 */
3119 u8 res_0c[500];/* 0x00c - 0x1ff */
3120 u32 l2pir0; /* 0x200 L2 cache partitioning ID register 0 */
3122 u32 l2par0; /* 0x208 L2 cache partitioning allocation register 0 */
3123 u32 l2pwr0; /* 0x20c L2 cache partitioning way register 0 */
3124 u32 l2pir1; /* 0x210 L2 cache partitioning ID register 1 */
3126 u32 l2par1; /* 0x218 L2 cache partitioning allocation register 1 */
3127 u32 l2pwr1; /* 0x21c L2 cache partitioning way register 1 */
3128 u32 u2pir2; /* 0x220 L2 cache partitioning ID register 2 */
3130 u32 l2par2; /* 0x228 L2 cache partitioning allocation register 2 */
3131 u32 l2pwr2; /* 0x22c L2 cache partitioning way register 2 */
3132 u32 l2pir3; /* 0x230 L2 cache partitioning ID register 3 */
3134 u32 l2par3; /* 0x238 L2 cache partitining allocation register 3 */
3135 u32 l2pwr3; /* 0x23c L2 cache partitining way register 3 */
3136 u32 l2pir4; /* 0x240 L2 cache partitioning ID register 3 */
3138 u32 l2par4; /* 0x248 L2 cache partitioning allocation register 3 */
3139 u32 l2pwr4; /* 0x24c L2 cache partitioning way register 3 */
3140 u32 l2pir5; /* 0x250 L2 cache partitioning ID register 3 */
3142 u32 l2par5; /* 0x258 L2 cache partitioning allocation register 3 */
3143 u32 l2pwr5; /* 0x25c L2 cache partitioning way register 3 */
3144 u32 l2pir6; /* 0x260 L2 cache partitioning ID register 3 */
3146 u32 l2par6; /* 0x268 L2 cache partitioning allocation register 3 */
3147 u32 l2pwr6; /* 0x26c L2 cache partitioning way register 3 */
3148 u32 l2pir7; /* 0x270 L2 cache partitioning ID register 3 */
3150 u32 l2par7; /* 0x278 L2 cache partitioning allocation register 3 */
3151 u32 l2pwr7; /* 0x27c L2 cache partitioning way register 3 */
3152 u8 res_280[0xb80]; /* 0x280 - 0xdff */
3153 u32 l2errinjhi; /* 0xe00 L2 cache error injection mask high */
3154 u32 l2errinjlo; /* 0xe04 L2 cache error injection mask low */
3155 u32 l2errinjctl;/* 0xe08 L2 cache error injection control */
3156 u8 res_e0c[20]; /* 0xe0c - 0x01f */
3157 u32 l2captdatahi; /* 0xe20 L2 cache error capture data high */
3158 u32 l2captdatalo; /* 0xe24 L2 cache error capture data low */
3159 u32 l2captecc; /* 0xe28 L2 cache error capture ECC syndrome */
3160 u8 res_e2c[20]; /* 0xe2c - 0xe3f */
3161 u32 l2errdet; /* 0xe40 L2 cache error detect */
3162 u32 l2errdis; /* 0xe44 L2 cache error disable */
3163 u32 l2errinten; /* 0xe48 L2 cache error interrupt enable */
3164 u32 l2errattr; /* 0xe4c L2 cache error attribute */
3165 u32 l2erreaddr; /* 0xe50 L2 cache error extended address */
3166 u32 l2erraddr; /* 0xe54 L2 cache error address */
3167 u32 l2errctl; /* 0xe58 L2 cache error control */
3173 #define CONFIG_SYS_DCSR_DCFG_OFFSET 0X20000
3175 u8 res_0[0x520];
3177 #define DCSR_DCFG_ECC_DISABLE_USB1 0x00008000
3178 #define DCSR_DCFG_ECC_DISABLE_USB2 0x00004000
3179 u8 res_524[0x1000 - 0x524]; /* 0x524 - 0x1000 */
3184 #define CONFIG_SYS_MPC85xx_SCFG_OFFSET 0xfc000
3187 u32 dpslpcr; /* 0x000 Deep Sleep Control register */
3188 u32 usb1dpslpcsr;/* 0x004 USB1 Deep Sleep Control Status register */
3189 u32 usb2dpslpcsr;/* 0x008 USB2 Deep Sleep Control Status register */
3190 u32 fmclkdpslpcr;/* 0x00c FM Clock Deep Sleep Control register */
3192 u32 esgmiiselcr;/* 0x020 Ethernet Switch SGMII Select Control reg */
3194 u32 pixclkcr; /* 0x028 Pixel Clock Control register */
3196 u32 qeioclkcr; /* 0x400 QUICC Engine IO Clock Control register */
3197 u32 emiiocr; /* 0x404 EMI MDIO Control Register */
3198 u32 sdhciovselcr;/* 0x408 SDHC IO VSEL Control register */
3199 u32 qmifrstcr; /* 0x40c QMAN Interface Reset Control register */
3201 u32 sparecr[8]; /* 0x500 Spare Control register(0-7) */