Lines Matching defs:immap
630 typedef struct immap { struct
631 sysconf83xx_t sysconf; /* System configuration */
632 wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
633 rtclk83xx_t rtc; /* Real Time Clock Module Registers */
634 rtclk83xx_t pit; /* Periodic Interval Timer */
635 gtm83xx_t gtm[2]; /* Global Timers Module */
636 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
637 arbiter83xx_t arbiter; /* System Arbiter Registers */
638 reset83xx_t reset; /* Reset Module */
639 clk83xx_t clk; /* System Clock Module */
640 pmc83xx_t pmc; /* Power Management Control Module */
641 gpio83xx_t gpio[2]; /* General purpose I/O module */
642 u8 res0[0x200];
643 u8 dll_ddr[0x100];
644 u8 dll_lbc[0x100];
668 } immap_t; argument
684 typedef struct immap { argument
685 sysconf83xx_t sysconf; /* System configuration */
686 wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
687 rtclk83xx_t rtc; /* Real Time Clock Module Registers */
688 rtclk83xx_t pit; /* Periodic Interval Timer */
689 gtm83xx_t gtm[2]; /* Global Timers Module */
690 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
691 arbiter83xx_t arbiter; /* System Arbiter Registers */
692 reset83xx_t reset; /* Reset Module */
716 } immap_t; argument
719 typedef struct immap { argument
720 sysconf83xx_t sysconf; /* System configuration */
721 wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
722 rtclk83xx_t rtc; /* Real Time Clock Module Registers */
723 rtclk83xx_t pit; /* Periodic Interval Timer */
724 gtm83xx_t gtm[2]; /* Global Timers Module */
725 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
726 arbiter83xx_t arbiter; /* System Arbiter Registers */
727 reset83xx_t reset; /* Reset Module */
728 clk83xx_t clk; /* System Clock Module */
729 pmc83xx_t pmc; /* Power Management Control Module */
730 gpio83xx_t gpio[1]; /* General purpose I/O module */
731 u8 res0[0x1300];
732 ddr83xx_t ddr; /* DDR Memory Controller Memory */
733 fsl_i2c_t i2c[2]; /* I2C Controllers */
734 u8 res1[0x1300];
735 duart83xx_t duart[2]; /* DUART */
736 u8 res2[0x900];
737 fsl_lbc_t im_lbc; /* Local Bus Controller Regs */
761 } immap_t; argument
764 typedef struct immap { argument
765 sysconf83xx_t sysconf; /* System configuration */
766 wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
767 rtclk83xx_t rtc; /* Real Time Clock Module Registers */
768 rtclk83xx_t pit; /* Periodic Interval Timer */
769 gtm83xx_t gtm[2]; /* Global Timers Module */
770 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
771 arbiter83xx_t arbiter; /* System Arbiter Registers */
772 reset83xx_t reset; /* Reset Module */
773 clk83xx_t clk; /* System Clock Module */
774 pmc83xx_t pmc; /* Power Management Control Module */
775 gpio83xx_t gpio[2]; /* General purpose I/O module */
776 u8 res0[0x1200];
777 ddr83xx_t ddr; /* DDR Memory Controller Memory */
778 fsl_i2c_t i2c[2]; /* I2C Controllers */
779 u8 res1[0x1300];
780 duart83xx_t duart[2]; /* DUART */
781 u8 res2[0x900];
805 } immap_t; argument
808 typedef struct immap { argument
809 sysconf83xx_t sysconf; /* System configuration */
810 wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
811 rtclk83xx_t rtc; /* Real Time Clock Module Registers */
812 rtclk83xx_t pit; /* Periodic Interval Timer */
813 u8 res0[0x200];
814 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
815 arbiter83xx_t arbiter; /* System Arbiter Registers */
816 reset83xx_t reset; /* Reset Module */
817 clk83xx_t clk; /* System Clock Module */
818 pmc83xx_t pmc; /* Power Management Control Module */
819 qepi83xx_t qepi; /* QE Ports Interrupts Registers */
820 u8 res1[0x300];
821 u8 dll_ddr[0x100];
845 } immap_t; argument
848 typedef struct immap { argument
849 sysconf83xx_t sysconf; /* System configuration */
850 wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
851 rtclk83xx_t rtc; /* Real Time Clock Module Registers */
852 rtclk83xx_t pit; /* Periodic Interval Timer */
853 gtm83xx_t gtm[2]; /* Global Timers Module */
854 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
855 arbiter83xx_t arbiter; /* System Arbiter Registers */
856 reset83xx_t reset; /* Reset Module */
857 clk83xx_t clk; /* System Clock Module */
858 pmc83xx_t pmc; /* Power Management Control Module */
882 } immap_t; argument
884 typedef struct immap { argument
885 sysconf83xx_t sysconf; /* System configuration */
886 wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
887 rtclk83xx_t rtc; /* Real Time Clock Module Registers */
888 rtclk83xx_t pit; /* Periodic Interval Timer */
889 gtm83xx_t gtm[2]; /* Global Timers Module */
890 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
891 arbiter83xx_t arbiter; /* System Arbiter Registers */
892 reset83xx_t reset; /* Reset Module */
893 clk83xx_t clk; /* System Clock Module */
894 pmc83xx_t pmc; /* Power Management Control Module */
895 gpio83xx_t gpio[2]; /* General purpose I/O module */
896 u8 res0[0x500]; /* res0 1.25 KBytes added for 8309 */
897 qepi83xx_t qepi; /* QE Ports Interrupts Registers */
898 qepio83xx_t qepio; /* QE Parallel I/O ports */
899 u8 res1[0x800];
900 ddr83xx_t ddr; /* DDR Memory Controller Memory */
901 fsl_i2c_t i2c[2]; /* I2C Controllers */
902 u8 res2[0x1300];
903 duart83xx_t duart[2]; /* DUART */
904 u8 res3[0x200];
905 duart83xx_t duart1[2]; /* DUART */
906 u8 res4[0x500];
907 fsl_lbc_t im_lbc; /* Local Bus Controller Regs */
908 u8 res5[0x1000];
932 } immap_t; argument