include/asm/cpm_8xx.h

63 #define BD_IIC_START	((uint) 0x0400) /* <- please use CPM_I2C_BASE !! */
75 	uint	cbd_bufaddr;	/* Buffer address in host memory */
95 #define PROFF_SCC1	((uint)0x0000)
96 #define PROFF_IIC	((uint)0x0080)
97 #define PROFF_REVNUM	((uint)0x00b0)
98 #define PROFF_SCC2	((uint)0x0100)
99 #define PROFF_SPI	((uint)0x0180)
100 #define PROFF_SCC3	((uint)0x0200)
101 #define PROFF_SMC1	((uint)0x0280)
102 #define PROFF_SCC4	((uint)0x0300)
103 #define PROFF_SMC2	((uint)0x0380)
113 	uint	smc_rstate;	/* Internal */
114 	uint	smc_idp;	/* Internal */
117 	uint	smc_rxtmp;	/* Internal */
118 	uint	smc_tstate;	/* Internal */
119 	uint	smc_tdp;	/* Internal */
122 	uint	smc_txtmp;	/* Internal */
165 	uint	scent_rstate;
166 	uint	scent_r_ptr;
169 	uint	scent_rtemp;
170 	uint	scent_tstate;
171 	uint	scent_t_ptr;
174 	uint	scent_ttemp;
206 #define CPM_BRG_RST		((uint)0x00020000)
207 #define CPM_BRG_EN		((uint)0x00010000)
208 #define CPM_BRG_EXTC_INT	((uint)0x00000000)
209 #define CPM_BRG_EXTC_CLK2	((uint)0x00004000)
210 #define CPM_BRG_EXTC_CLK6	((uint)0x00008000)
211 #define CPM_BRG_ATB		((uint)0x00002000)
212 #define CPM_BRG_CD_MASK		((uint)0x00001ffe)
213 #define CPM_BRG_DIV16		((uint)0x00000001)
217 #define SICR_RCLK_SCC1_BRG1	((uint)0x00000000)
218 #define SICR_TCLK_SCC1_BRG1	((uint)0x00000000)
219 #define SICR_RCLK_SCC2_BRG2	((uint)0x00000800)
220 #define SICR_TCLK_SCC2_BRG2	((uint)0x00000100)
221 #define SICR_RCLK_SCC3_BRG3	((uint)0x00100000)
222 #define SICR_TCLK_SCC3_BRG3	((uint)0x00020000)
223 #define SICR_RCLK_SCC4_BRG4	((uint)0x18000000)
224 #define SICR_TCLK_SCC4_BRG4	((uint)0x03000000)
228 #define SCC_GSMRH_IRP		((uint)0x00040000)
229 #define SCC_GSMRH_GDE		((uint)0x00010000)
230 #define SCC_GSMRH_TCRC_CCITT	((uint)0x00008000)
231 #define SCC_GSMRH_TCRC_BISYNC	((uint)0x00004000)
232 #define SCC_GSMRH_TCRC_HDLC	((uint)0x00000000)
233 #define SCC_GSMRH_REVD		((uint)0x00002000)
234 #define SCC_GSMRH_TRX		((uint)0x00001000)
235 #define SCC_GSMRH_TTX		((uint)0x00000800)
236 #define SCC_GSMRH_CDP		((uint)0x00000400)
237 #define SCC_GSMRH_CTSP		((uint)0x00000200)
238 #define SCC_GSMRH_CDS		((uint)0x00000100)
239 #define SCC_GSMRH_CTSS		((uint)0x00000080)
240 #define SCC_GSMRH_TFL		((uint)0x00000040)
241 #define SCC_GSMRH_RFW		((uint)0x00000020)
242 #define SCC_GSMRH_TXSY		((uint)0x00000010)
243 #define SCC_GSMRH_SYNL16	((uint)0x0000000c)
244 #define SCC_GSMRH_SYNL8		((uint)0x00000008)
245 #define SCC_GSMRH_SYNL4		((uint)0x00000004)
246 #define SCC_GSMRH_RTSM		((uint)0x00000002)
247 #define SCC_GSMRH_RSYN		((uint)0x00000001)
249 #define SCC_GSMRL_SIR		((uint)0x80000000)	/* SCC2 only */
250 #define SCC_GSMRL_EDGE_NONE	((uint)0x60000000)
251 #define SCC_GSMRL_EDGE_NEG	((uint)0x40000000)
252 #define SCC_GSMRL_EDGE_POS	((uint)0x20000000)
253 #define SCC_GSMRL_EDGE_BOTH	((uint)0x00000000)
254 #define SCC_GSMRL_TCI		((uint)0x10000000)
255 #define SCC_GSMRL_TSNC_3	((uint)0x0c000000)
256 #define SCC_GSMRL_TSNC_4	((uint)0x08000000)
257 #define SCC_GSMRL_TSNC_14	((uint)0x04000000)
258 #define SCC_GSMRL_TSNC_INF	((uint)0x00000000)
259 #define SCC_GSMRL_RINV		((uint)0x02000000)
260 #define SCC_GSMRL_TINV		((uint)0x01000000)
261 #define SCC_GSMRL_TPL_128	((uint)0x00c00000)
262 #define SCC_GSMRL_TPL_64	((uint)0x00a00000)
263 #define SCC_GSMRL_TPL_48	((uint)0x00800000)
264 #define SCC_GSMRL_TPL_32	((uint)0x00600000)
265 #define SCC_GSMRL_TPL_16	((uint)0x00400000)
266 #define SCC_GSMRL_TPL_8		((uint)0x00200000)
267 #define SCC_GSMRL_TPL_NONE	((uint)0x00000000)
268 #define SCC_GSMRL_TPP_ALL1	((uint)0x00180000)
269 #define SCC_GSMRL_TPP_01	((uint)0x00100000)
270 #define SCC_GSMRL_TPP_10	((uint)0x00080000)
271 #define SCC_GSMRL_TPP_ZEROS	((uint)0x00000000)
272 #define SCC_GSMRL_TEND		((uint)0x00040000)
273 #define SCC_GSMRL_TDCR_32	((uint)0x00030000)
274 #define SCC_GSMRL_TDCR_16	((uint)0x00020000)
275 #define SCC_GSMRL_TDCR_8	((uint)0x00010000)
276 #define SCC_GSMRL_TDCR_1	((uint)0x00000000)
277 #define SCC_GSMRL_RDCR_32	((uint)0x0000c000)
278 #define SCC_GSMRL_RDCR_16	((uint)0x00008000)
279 #define SCC_GSMRL_RDCR_8	((uint)0x00004000)
280 #define SCC_GSMRL_RDCR_1	((uint)0x00000000)
281 #define SCC_GSMRL_RENC_DFMAN	((uint)0x00003000)
282 #define SCC_GSMRL_RENC_MANCH	((uint)0x00002000)
283 #define SCC_GSMRL_RENC_FM0	((uint)0x00001000)
284 #define SCC_GSMRL_RENC_NRZI	((uint)0x00000800)
285 #define SCC_GSMRL_RENC_NRZ	((uint)0x00000000)
286 #define SCC_GSMRL_TENC_DFMAN	((uint)0x00000600)
287 #define SCC_GSMRL_TENC_MANCH	((uint)0x00000400)
288 #define SCC_GSMRL_TENC_FM0	((uint)0x00000200)
289 #define SCC_GSMRL_TENC_NRZI	((uint)0x00000100)
290 #define SCC_GSMRL_TENC_NRZ	((uint)0x00000000)
291 #define SCC_GSMRL_DIAG_LE	((uint)0x000000c0)	/* Loop and echo */
292 #define SCC_GSMRL_DIAG_ECHO	((uint)0x00000080)
293 #define SCC_GSMRL_DIAG_LOOP	((uint)0x00000040)
294 #define SCC_GSMRL_DIAG_NORM	((uint)0x00000000)
295 #define SCC_GSMRL_ENR		((uint)0x00000020)
296 #define SCC_GSMRL_ENT		((uint)0x00000010)
297 #define SCC_GSMRL_MODE_ENET	((uint)0x0000000c)
298 #define SCC_GSMRL_MODE_DDCMP	((uint)0x00000009)
299 #define SCC_GSMRL_MODE_BISYNC	((uint)0x00000008)
300 #define SCC_GSMRL_MODE_V14	((uint)0x00000007)
301 #define SCC_GSMRL_MODE_AHDLC	((uint)0x00000006)
302 #define SCC_GSMRL_MODE_PROFIBUS	((uint)0x00000005)
303 #define SCC_GSMRL_MODE_UART	((uint)0x00000004)
304 #define SCC_GSMRL_MODE_SS7	((uint)0x00000003)
305 #define SCC_GSMRL_MODE_ATALK	((uint)0x00000002)
306 #define SCC_GSMRL_MODE_HDLC	((uint)0x00000000)
323 	uint	scc_rstate;	/* Internal */
324 	uint	scc_idp;	/* Internal */
327 	uint	scc_rxtmp;	/* Internal */
328 	uint	scc_tstate;	/* Internal */
329 	uint	scc_tdp;	/* Internal */
332 	uint	scc_txtmp;	/* Internal */
333 	uint	scc_rcrc;	/* Internal */
334 	uint	scc_tcrc;	/* Internal */
345 	uint	sen_cpres;	/* Preset CRC */
346 	uint	sen_cmask;	/* Constant mask for CRC */
347 	uint	sen_crcec;	/* CRC Error counter */
348 	uint	sen_alec;	/* alignment error counter */
349 	uint	sen_disfc;	/* discard frame counter */
364 	uint	sen_tbuf0data0;	/* Save area 0 - current frame */
365 	uint	sen_tbuf0data1;	/* Save area 1 - current frame */
366 	uint	sen_tbuf0rba;	/* Internal */
367 	uint	sen_tbuf0crc;	/* Internal */
376 	uint	sen_tbuf1data0;	/* Save area 0 - current frame */
377 	uint	sen_tbuf1data1;	/* Save area 1 - current frame */
378 	uint	sen_tbuf1rba;	/* Internal */
379 	uint	sen_tbuf1crc;	/* Internal */
460 	uint	scc_res1;	/* Reserved */
461 	uint	scc_res2;	/* Reserved */
521 	uint	st_cpres;	/* Preset CRC */
522 	uint	st_cmask;	/* Constant mask for CRC */
535 	uint	iic_rstate;	/* Internal */
536 	uint	iic_rdp;	/* Internal */
539 	uint	iic_rxtmp;	/* Internal */
540 	uint	iic_tstate;	/* Internal */
541 	uint	iic_tdp;	/* Internal */
544 	uint	iic_txtmp;	/* Internal */
545 	uint	iic_res;	/* reserved */
558 	uint	spi_rstate;	/* Internal */
559 	uint	spi_rdp;	/* Internal */
562 	uint	spi_rxtmp;	/* Internal */
563 	uint	spi_tstate;	/* Internal */
564 	uint	spi_tdp;	/* Internal */
567 	uint	spi_txtmp;	/* Internal */
568 	uint	spi_res;
679 #define	CICR_SCD_SCC4		((uint)0x00c00000)	/* SCC4 @ SCCd */
680 #define	CICR_SCC_SCC3		((uint)0x00200000)	/* SCC3 @ SCCc */
681 #define	CICR_SCB_SCC2		((uint)0x00040000)	/* SCC2 @ SCCb */
682 #define	CICR_SCA_SCC1		((uint)0x00000000)	/* SCC1 @ SCCa */
683 #define CICR_IRL_MASK		((uint)0x0000e000)	/* Core interrupt */
684 #define CICR_HP_MASK		((uint)0x00001f00)	/* Hi-pri int. */
685 #define CICR_IEN		((uint)0x00000080)	/* Int. enable */
686 #define CICR_SPS		((uint)0x00000001)	/* SCC Spread */