include/asm/cpm_85xx.h

21 #define CPM_CR_RST	((uint)0x80000000)
22 #define CPM_CR_PAGE	((uint)0x7c000000)
23 #define CPM_CR_SBLOCK	((uint)0x03e00000)
24 #define CPM_CR_FLG	((uint)0x00010000)
25 #define CPM_CR_MCN	((uint)0x00003fc0)
26 #define CPM_CR_OPCODE	((uint)0x0000000f)
78 #define CPM_DATAONLY_BASE	((uint)128)
79 #define CPM_DP_NOSPACE		((uint)0x7FFFFFFF)
81 #define CPM_FCC_SPECIAL_BASE	((uint)0x00009000)
82 #define CPM_DATAONLY_SIZE	((uint)(8 * 1024) - CPM_DATAONLY_BASE)
84 #define CPM_FCC_SPECIAL_BASE	((uint)0x0000B000)
85 #define CPM_DATAONLY_SIZE	((uint)(16 * 1024) - CPM_DATAONLY_BASE)
98 uint		m8560_cpm_dpalloc(uint size, uint align);
99 uint		m8560_cpm_hostalloc(uint size, uint align);
100 void		m8560_cpm_setbrg(uint brg, uint rate);
101 void		m8560_cpm_fastbrg(uint brg, uint rate, int div16);
102 void		m8560_cpm_extcbrg(uint brg, uint rate, uint extclk, int pinsel);
109 	uint	cbd_bufaddr;	/* Buffer address in host memory */
137 #define PROFF_SCC1		((uint)0x8000)
138 #define PROFF_SCC2		((uint)0x8100)
139 #define PROFF_SCC3		((uint)0x8200)
140 #define PROFF_SCC4		((uint)0x8300)
141 #define PROFF_FCC1		((uint)0x8400)
142 #define PROFF_FCC2		((uint)0x8500)
143 #define PROFF_FCC3		((uint)0x8600)
144 #define PROFF_MCC1		((uint)0x8700)
145 #define PROFF_MCC2		((uint)0x8800)
146 #define PROFF_SPI_BASE		((uint)0x89fc)
147 #define PROFF_TIMERS		((uint)0x8ae0)
148 #define PROFF_REVNUM		((uint)0x8af0)
149 #define PROFF_RAND		((uint)0x8af8)
150 #define PROFF_I2C_BASE		((uint)0x8afc)
154 #define CPM_BRG_RST		((uint)0x00020000)
155 #define CPM_BRG_EN		((uint)0x00010000)
156 #define CPM_BRG_EXTC_INT	((uint)0x00000000)
157 #define CPM_BRG_EXTC_CLK3_9	((uint)0x00004000)
158 #define CPM_BRG_EXTC_CLK5_15	((uint)0x00008000)
159 #define CPM_BRG_ATB		((uint)0x00002000)
160 #define CPM_BRG_CD_MASK		((uint)0x00001ffe)
161 #define CPM_BRG_DIV16		((uint)0x00000001)
165 #define SCC_GSMRH_IRP		((uint)0x00040000)
166 #define SCC_GSMRH_GDE		((uint)0x00010000)
167 #define SCC_GSMRH_TCRC_CCITT	((uint)0x00008000)
168 #define SCC_GSMRH_TCRC_BISYNC	((uint)0x00004000)
169 #define SCC_GSMRH_TCRC_HDLC	((uint)0x00000000)
170 #define SCC_GSMRH_REVD		((uint)0x00002000)
171 #define SCC_GSMRH_TRX		((uint)0x00001000)
172 #define SCC_GSMRH_TTX		((uint)0x00000800)
173 #define SCC_GSMRH_CDP		((uint)0x00000400)
174 #define SCC_GSMRH_CTSP		((uint)0x00000200)
175 #define SCC_GSMRH_CDS		((uint)0x00000100)
176 #define SCC_GSMRH_CTSS		((uint)0x00000080)
177 #define SCC_GSMRH_TFL		((uint)0x00000040)
178 #define SCC_GSMRH_RFW		((uint)0x00000020)
179 #define SCC_GSMRH_TXSY		((uint)0x00000010)
180 #define SCC_GSMRH_SYNL16	((uint)0x0000000c)
181 #define SCC_GSMRH_SYNL8		((uint)0x00000008)
182 #define SCC_GSMRH_SYNL4		((uint)0x00000004)
183 #define SCC_GSMRH_RTSM		((uint)0x00000002)
184 #define SCC_GSMRH_RSYN		((uint)0x00000001)
186 #define SCC_GSMRL_SIR		((uint)0x80000000)	/* SCC2 only */
187 #define SCC_GSMRL_EDGE_NONE	((uint)0x60000000)
188 #define SCC_GSMRL_EDGE_NEG	((uint)0x40000000)
189 #define SCC_GSMRL_EDGE_POS	((uint)0x20000000)
190 #define SCC_GSMRL_EDGE_BOTH	((uint)0x00000000)
191 #define SCC_GSMRL_TCI		((uint)0x10000000)
192 #define SCC_GSMRL_TSNC_3	((uint)0x0c000000)
193 #define SCC_GSMRL_TSNC_4	((uint)0x08000000)
194 #define SCC_GSMRL_TSNC_14	((uint)0x04000000)
195 #define SCC_GSMRL_TSNC_INF	((uint)0x00000000)
196 #define SCC_GSMRL_RINV		((uint)0x02000000)
197 #define SCC_GSMRL_TINV		((uint)0x01000000)
198 #define SCC_GSMRL_TPL_128	((uint)0x00c00000)
199 #define SCC_GSMRL_TPL_64	((uint)0x00a00000)
200 #define SCC_GSMRL_TPL_48	((uint)0x00800000)
201 #define SCC_GSMRL_TPL_32	((uint)0x00600000)
202 #define SCC_GSMRL_TPL_16	((uint)0x00400000)
203 #define SCC_GSMRL_TPL_8		((uint)0x00200000)
204 #define SCC_GSMRL_TPL_NONE	((uint)0x00000000)
205 #define SCC_GSMRL_TPP_ALL1	((uint)0x00180000)
206 #define SCC_GSMRL_TPP_01	((uint)0x00100000)
207 #define SCC_GSMRL_TPP_10	((uint)0x00080000)
208 #define SCC_GSMRL_TPP_ZEROS	((uint)0x00000000)
209 #define SCC_GSMRL_TEND		((uint)0x00040000)
210 #define SCC_GSMRL_TDCR_32	((uint)0x00030000)
211 #define SCC_GSMRL_TDCR_16	((uint)0x00020000)
212 #define SCC_GSMRL_TDCR_8	((uint)0x00010000)
213 #define SCC_GSMRL_TDCR_1	((uint)0x00000000)
214 #define SCC_GSMRL_RDCR_32	((uint)0x0000c000)
215 #define SCC_GSMRL_RDCR_16	((uint)0x00008000)
216 #define SCC_GSMRL_RDCR_8	((uint)0x00004000)
217 #define SCC_GSMRL_RDCR_1	((uint)0x00000000)
218 #define SCC_GSMRL_RENC_DFMAN	((uint)0x00003000)
219 #define SCC_GSMRL_RENC_MANCH	((uint)0x00002000)
220 #define SCC_GSMRL_RENC_FM0	((uint)0x00001000)
221 #define SCC_GSMRL_RENC_NRZI	((uint)0x00000800)
222 #define SCC_GSMRL_RENC_NRZ	((uint)0x00000000)
223 #define SCC_GSMRL_TENC_DFMAN	((uint)0x00000600)
224 #define SCC_GSMRL_TENC_MANCH	((uint)0x00000400)
225 #define SCC_GSMRL_TENC_FM0	((uint)0x00000200)
226 #define SCC_GSMRL_TENC_NRZI	((uint)0x00000100)
227 #define SCC_GSMRL_TENC_NRZ	((uint)0x00000000)
228 #define SCC_GSMRL_DIAG_LE	((uint)0x000000c0)	/* Loop and echo */
229 #define SCC_GSMRL_DIAG_ECHO	((uint)0x00000080)
230 #define SCC_GSMRL_DIAG_LOOP	((uint)0x00000040)
231 #define SCC_GSMRL_DIAG_NORM	((uint)0x00000000)
232 #define SCC_GSMRL_ENR		((uint)0x00000020)
233 #define SCC_GSMRL_ENT		((uint)0x00000010)
234 #define SCC_GSMRL_MODE_ENET	((uint)0x0000000c)
235 #define SCC_GSMRL_MODE_DDCMP	((uint)0x00000009)
236 #define SCC_GSMRL_MODE_BISYNC	((uint)0x00000008)
237 #define SCC_GSMRL_MODE_V14	((uint)0x00000007)
238 #define SCC_GSMRL_MODE_AHDLC	((uint)0x00000006)
239 #define SCC_GSMRL_MODE_PROFIBUS	((uint)0x00000005)
240 #define SCC_GSMRL_MODE_UART	((uint)0x00000004)
241 #define SCC_GSMRL_MODE_SS7	((uint)0x00000003)
242 #define SCC_GSMRL_MODE_ATALK	((uint)0x00000002)
243 #define SCC_GSMRL_MODE_HDLC	((uint)0x00000000)
260 	uint	scc_rstate;	/* Internal */
261 	uint	scc_idp;	/* Internal */
264 	uint	scc_rxtmp;	/* Internal */
265 	uint	scc_tstate;	/* Internal */
266 	uint	scc_tdp;	/* Internal */
269 	uint	scc_txtmp;	/* Internal */
270 	uint	scc_rcrc;	/* Internal */
271 	uint	scc_tcrc;	/* Internal */
278 	uint	sen_cpres;	/* Preset CRC */
279 	uint	sen_cmask;	/* Constant mask for CRC */
280 	uint	sen_crcec;	/* CRC Error counter */
281 	uint	sen_alec;	/* alignment error counter */
282 	uint	sen_disfc;	/* discard frame counter */
297 	uint	sen_tbuf0data0;	/* Save area 0 - current frame */
298 	uint	sen_tbuf0data1;	/* Save area 1 - current frame */
299 	uint	sen_tbuf0rba;	/* Internal */
300 	uint	sen_tbuf0crc;	/* Internal */
309 	uint	sen_tbuf1data0;	/* Save area 0 - current frame */
310 	uint	sen_tbuf1data1;	/* Save area 1 - current frame */
311 	uint	sen_tbuf1rba;	/* Internal */
312 	uint	sen_tbuf1crc;	/* Internal */
396 	uint	scc_res1;	/* Reserved */
397 	uint	scc_res2;	/* Reserved */
457 	uint	st_cpres;	/* Preset CRC */
458 	uint	st_cmask;	/* Constant mask for CRC */
465 #define FCC_GFMR_DIAG_NORM	((uint)0x00000000)
466 #define FCC_GFMR_DIAG_LE	((uint)0x40000000)
467 #define FCC_GFMR_DIAG_AE	((uint)0x80000000)
468 #define FCC_GFMR_DIAG_ALE	((uint)0xc0000000)
469 #define FCC_GFMR_TCI		((uint)0x20000000)
470 #define FCC_GFMR_TRX		((uint)0x10000000)
471 #define FCC_GFMR_TTX		((uint)0x08000000)
472 #define FCC_GFMR_TTX		((uint)0x08000000)
473 #define FCC_GFMR_CDP		((uint)0x04000000)
474 #define FCC_GFMR_CTSP		((uint)0x02000000)
475 #define FCC_GFMR_CDS		((uint)0x01000000)
476 #define FCC_GFMR_CTSS		((uint)0x00800000)
477 #define FCC_GFMR_SYNL_NONE	((uint)0x00000000)
478 #define FCC_GFMR_SYNL_AUTO	((uint)0x00004000)
479 #define FCC_GFMR_SYNL_8		((uint)0x00008000)
480 #define FCC_GFMR_SYNL_16	((uint)0x0000c000)
481 #define FCC_GFMR_RTSM		((uint)0x00002000)
482 #define FCC_GFMR_RENC_NRZ	((uint)0x00000000)
483 #define FCC_GFMR_RENC_NRZI	((uint)0x00000800)
484 #define FCC_GFMR_REVD		((uint)0x00000400)
485 #define FCC_GFMR_TENC_NRZ	((uint)0x00000000)
486 #define FCC_GFMR_TENC_NRZI	((uint)0x00000100)
487 #define FCC_GFMR_TCRC_16	((uint)0x00000000)
488 #define FCC_GFMR_TCRC_32	((uint)0x00000080)
489 #define FCC_GFMR_ENR		((uint)0x00000020)
490 #define FCC_GFMR_ENT		((uint)0x00000010)
491 #define FCC_GFMR_MODE_ENET	((uint)0x0000000c)
492 #define FCC_GFMR_MODE_ATM	((uint)0x0000000a)
493 #define FCC_GFMR_MODE_HDLC	((uint)0x00000000)
502 	uint	fcc_rstate;	/* Upper byte is Func code, must be set */
503 	uint	fcc_rbase;	/* Receive BD base */
506 	uint	fcc_rdptr;	/* RxBD internal data pointer */
507 	uint	fcc_tstate;	/* Upper byte is Func code, must be set */
508 	uint	fcc_tbase;	/* Transmit BD base */
511 	uint	fcc_tdptr;	/* TxBD internal data pointer */
512 	uint	fcc_rbptr;	/* Rx BD Internal buf pointer */
513 	uint	fcc_tbptr;	/* Tx BD Internal buf pointer */
514 	uint	fcc_rcrc;	/* Rx temp CRC */
515 	uint	fcc_res2;
516 	uint	fcc_tcrc;	/* Tx temp CRC */
524 	uint	fen_statbuf;	/* Internal status buffer */
525 	uint	fen_camptr;	/* CAM address */
526 	uint	fen_cmask;	/* Constant mask for CRC */
527 	uint	fen_cpres;	/* Preset CRC */
528 	uint	fen_crcec;	/* CRC Error counter */
529 	uint	fen_alec;	/* alignment error counter */
530 	uint	fen_disfc;	/* discard frame counter */
535 	uint	fen_gaddrh;	/* Group address filter, high 32-bits */
536 	uint	fen_gaddrl;	/* Group address filter, low 32-bits */
539 	uint	fen_tfcptr;
548 	uint	fen_ibdbase[8]; /* Internal use */
549 	uint	fen_iaddrh;	/* Individual address filter */
550 	uint	fen_iaddrl;
563 	uint	fen_octc;	/* Total octect counter */
564 	uint	fen_colc;	/* Total collision counter */
565 	uint	fen_broc;	/* Total broadcast packet counter */
566 	uint	fen_mulc;	/* Total multicast packet count */
567 	uint	fen_uspc;	/* Total packets < 64 bytes */
568 	uint	fen_frgc;	/* Total packets < 64 bytes with errors */
569 	uint	fen_ospc;	/* Total packets > 1518 */
570 	uint	fen_jbrc;	/* Total packets > 1518 with errors */
571 	uint	fen_p64c;	/* Total packets == 64 bytes */
572 	uint	fen_p65c;	/* Total packets 64 < bytes <= 127 */
573 	uint	fen_p128c;	/* Total packets 127 < bytes <= 255 */
574 	uint	fen_p256c;	/* Total packets 256 < bytes <= 511 */
575 	uint	fen_p512c;	/* Total packets 512 < bytes <= 1023 */
576 	uint	fen_p1024c;	/* Total packets 1024 < bytes <= 1518 */
577 	uint	fen_cambuf;	/* Internal CAM buffer poiner */
595 #define FCC_PSMR_HBC	((uint)0x80000000)	/* Enable heartbeat */
596 #define FCC_PSMR_FC	((uint)0x40000000)	/* Force Collision */
597 #define FCC_PSMR_SBT	((uint)0x20000000)	/* Stop backoff timer */
598 #define FCC_PSMR_LPB	((uint)0x10000000)	/* Local protect. 1 = FDX */
599 #define FCC_PSMR_LCW	((uint)0x08000000)	/* Late collision select */
600 #define FCC_PSMR_FDE	((uint)0x04000000)	/* Full Duplex Enable */
601 #define FCC_PSMR_MON	((uint)0x02000000)	/* RMON Enable */
602 #define FCC_PSMR_PRO	((uint)0x00400000)	/* Promiscuous Enable */
603 #define FCC_PSMR_FCE	((uint)0x00200000)	/* Flow Control Enable */
604 #define FCC_PSMR_RSH	((uint)0x00100000)	/* Receive Short Frames */
605 #define FCC_PSMR_CAM	((uint)0x00000400)	/* CAM enable */
606 #define FCC_PSMR_BRO	((uint)0x00000200)	/* Broadcast pkt discard */
607 #define FCC_PSMR_ENCRC	((uint)0x00000080)	/* Use 32-bit CRC */
617 	uint	iic_rstate;	/* Internal */
618 	uint	iic_rdp;	/* Internal */
621 	uint	iic_rxtmp;	/* Internal */
622 	uint	iic_tstate;	/* Internal */
623 	uint	iic_tdp;	/* Internal */
626 	uint	iic_txtmp;	/* Internal */
637 	uint	spi_rstate;	/* Internal */
638 	uint	spi_rdp;	/* Internal */
641 	uint	spi_rxtmp;	/* Internal */
642 	uint	spi_tstate;	/* Internal */
643 	uint	spi_tdp;	/* Internal */
646 	uint	spi_txtmp;	/* Internal */
647 	uint	spi_res;	/* Tx temp. */
648 	uint	spi_res1[4];	/* SDMA temp. */