Lines Matching +full:0 +full:x07000000
21 #define CPM_CR_RST ((uint)0x80000000)
22 #define CPM_CR_PAGE ((uint)0x7c000000)
23 #define CPM_CR_SBLOCK ((uint)0x03e00000)
24 #define CPM_CR_FLG ((uint)0x00010000)
25 #define CPM_CR_MCN ((uint)0x00003fc0)
26 #define CPM_CR_OPCODE ((uint)0x0000000f)
30 #define CPM_CR_SCC1_SBLOCK (0x04)
31 #define CPM_CR_SCC2_SBLOCK (0x05)
32 #define CPM_CR_SCC3_SBLOCK (0x06)
33 #define CPM_CR_SCC4_SBLOCK (0x07)
34 #define CPM_CR_SMC1_SBLOCK (0x08)
35 #define CPM_CR_SMC2_SBLOCK (0x09)
36 #define CPM_CR_SPI_SBLOCK (0x0a)
37 #define CPM_CR_I2C_SBLOCK (0x0b)
38 #define CPM_CR_TIMER_SBLOCK (0x0f)
39 #define CPM_CR_RAND_SBLOCK (0x0e)
40 #define CPM_CR_FCC1_SBLOCK (0x10)
41 #define CPM_CR_FCC2_SBLOCK (0x11)
42 #define CPM_CR_FCC3_SBLOCK (0x12)
43 #define CPM_CR_MCC1_SBLOCK (0x1c)
45 #define CPM_CR_SCC1_PAGE (0x00)
46 #define CPM_CR_SCC2_PAGE (0x01)
47 #define CPM_CR_SCC3_PAGE (0x02)
48 #define CPM_CR_SCC4_PAGE (0x03)
49 #define CPM_CR_SPI_PAGE (0x09)
50 #define CPM_CR_I2C_PAGE (0x0a)
51 #define CPM_CR_TIMER_PAGE (0x0a)
52 #define CPM_CR_RAND_PAGE (0x0a)
53 #define CPM_CR_FCC1_PAGE (0x04)
54 #define CPM_CR_FCC2_PAGE (0x05)
55 #define CPM_CR_FCC3_PAGE (0x06)
56 #define CPM_CR_MCC1_PAGE (0x07)
57 #define CPM_CR_MCC2_PAGE (0x08)
61 #define CPM_CR_INIT_TRX ((ushort)0x0000)
62 #define CPM_CR_INIT_RX ((ushort)0x0001)
63 #define CPM_CR_INIT_TX ((ushort)0x0002)
64 #define CPM_CR_HUNT_MODE ((ushort)0x0003)
65 #define CPM_CR_STOP_TX ((ushort)0x0004)
66 #define CPM_CR_RESTART_TX ((ushort)0x0006)
67 #define CPM_CR_SET_GADDR ((ushort)0x0008)
79 #define CPM_DP_NOSPACE ((uint)0x7FFFFFFF)
81 #define CPM_FCC_SPECIAL_BASE ((uint)0x00009000)
84 #define CPM_FCC_SPECIAL_BASE ((uint)0x0000B000)
112 #define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */
113 #define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */
114 #define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */
115 #define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */
116 #define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */
117 #define BD_SC_CM ((ushort)0x0200) /* Continous mode */
118 #define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */
119 #define BD_SC_P ((ushort)0x0100) /* xmt preamble */
120 #define BD_SC_BR ((ushort)0x0020) /* Break received */
121 #define BD_SC_FR ((ushort)0x0010) /* Framing error */
122 #define BD_SC_PR ((ushort)0x0008) /* Parity error */
123 #define BD_SC_OV ((ushort)0x0002) /* Overrun */
124 #define BD_SC_CD ((ushort)0x0001) /* ?? */
128 #define CPMFCR_GBL ((u_char)0x20) /* Set memory snooping */
129 #define CPMFCR_EB ((u_char)0x10) /* Set big endian byte order */
130 #define CPMFCR_TC2 ((u_char)0x04) /* Transfer code 2 value */
131 #define CPMFCR_DTB ((u_char)0x02) /* Use local bus for data when set */
132 #define CPMFCR_BDB ((u_char)0x01) /* Use local bus for BD when set */
136 #define CPM_POST_WORD_ADDR 0x80FC /* steal a long at the end of SCC1 */
137 #define PROFF_SCC1 ((uint)0x8000)
138 #define PROFF_SCC2 ((uint)0x8100)
139 #define PROFF_SCC3 ((uint)0x8200)
140 #define PROFF_SCC4 ((uint)0x8300)
141 #define PROFF_FCC1 ((uint)0x8400)
142 #define PROFF_FCC2 ((uint)0x8500)
143 #define PROFF_FCC3 ((uint)0x8600)
144 #define PROFF_MCC1 ((uint)0x8700)
145 #define PROFF_MCC2 ((uint)0x8800)
146 #define PROFF_SPI_BASE ((uint)0x89fc)
147 #define PROFF_TIMERS ((uint)0x8ae0)
148 #define PROFF_REVNUM ((uint)0x8af0)
149 #define PROFF_RAND ((uint)0x8af8)
150 #define PROFF_I2C_BASE ((uint)0x8afc)
154 #define CPM_BRG_RST ((uint)0x00020000)
155 #define CPM_BRG_EN ((uint)0x00010000)
156 #define CPM_BRG_EXTC_INT ((uint)0x00000000)
157 #define CPM_BRG_EXTC_CLK3_9 ((uint)0x00004000)
158 #define CPM_BRG_EXTC_CLK5_15 ((uint)0x00008000)
159 #define CPM_BRG_ATB ((uint)0x00002000)
160 #define CPM_BRG_CD_MASK ((uint)0x00001ffe)
161 #define CPM_BRG_DIV16 ((uint)0x00000001)
165 #define SCC_GSMRH_IRP ((uint)0x00040000)
166 #define SCC_GSMRH_GDE ((uint)0x00010000)
167 #define SCC_GSMRH_TCRC_CCITT ((uint)0x00008000)
168 #define SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000)
169 #define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000)
170 #define SCC_GSMRH_REVD ((uint)0x00002000)
171 #define SCC_GSMRH_TRX ((uint)0x00001000)
172 #define SCC_GSMRH_TTX ((uint)0x00000800)
173 #define SCC_GSMRH_CDP ((uint)0x00000400)
174 #define SCC_GSMRH_CTSP ((uint)0x00000200)
175 #define SCC_GSMRH_CDS ((uint)0x00000100)
176 #define SCC_GSMRH_CTSS ((uint)0x00000080)
177 #define SCC_GSMRH_TFL ((uint)0x00000040)
178 #define SCC_GSMRH_RFW ((uint)0x00000020)
179 #define SCC_GSMRH_TXSY ((uint)0x00000010)
180 #define SCC_GSMRH_SYNL16 ((uint)0x0000000c)
181 #define SCC_GSMRH_SYNL8 ((uint)0x00000008)
182 #define SCC_GSMRH_SYNL4 ((uint)0x00000004)
183 #define SCC_GSMRH_RTSM ((uint)0x00000002)
184 #define SCC_GSMRH_RSYN ((uint)0x00000001)
186 #define SCC_GSMRL_SIR ((uint)0x80000000) /* SCC2 only */
187 #define SCC_GSMRL_EDGE_NONE ((uint)0x60000000)
188 #define SCC_GSMRL_EDGE_NEG ((uint)0x40000000)
189 #define SCC_GSMRL_EDGE_POS ((uint)0x20000000)
190 #define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000)
191 #define SCC_GSMRL_TCI ((uint)0x10000000)
192 #define SCC_GSMRL_TSNC_3 ((uint)0x0c000000)
193 #define SCC_GSMRL_TSNC_4 ((uint)0x08000000)
194 #define SCC_GSMRL_TSNC_14 ((uint)0x04000000)
195 #define SCC_GSMRL_TSNC_INF ((uint)0x00000000)
196 #define SCC_GSMRL_RINV ((uint)0x02000000)
197 #define SCC_GSMRL_TINV ((uint)0x01000000)
198 #define SCC_GSMRL_TPL_128 ((uint)0x00c00000)
199 #define SCC_GSMRL_TPL_64 ((uint)0x00a00000)
200 #define SCC_GSMRL_TPL_48 ((uint)0x00800000)
201 #define SCC_GSMRL_TPL_32 ((uint)0x00600000)
202 #define SCC_GSMRL_TPL_16 ((uint)0x00400000)
203 #define SCC_GSMRL_TPL_8 ((uint)0x00200000)
204 #define SCC_GSMRL_TPL_NONE ((uint)0x00000000)
205 #define SCC_GSMRL_TPP_ALL1 ((uint)0x00180000)
206 #define SCC_GSMRL_TPP_01 ((uint)0x00100000)
207 #define SCC_GSMRL_TPP_10 ((uint)0x00080000)
208 #define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000)
209 #define SCC_GSMRL_TEND ((uint)0x00040000)
210 #define SCC_GSMRL_TDCR_32 ((uint)0x00030000)
211 #define SCC_GSMRL_TDCR_16 ((uint)0x00020000)
212 #define SCC_GSMRL_TDCR_8 ((uint)0x00010000)
213 #define SCC_GSMRL_TDCR_1 ((uint)0x00000000)
214 #define SCC_GSMRL_RDCR_32 ((uint)0x0000c000)
215 #define SCC_GSMRL_RDCR_16 ((uint)0x00008000)
216 #define SCC_GSMRL_RDCR_8 ((uint)0x00004000)
217 #define SCC_GSMRL_RDCR_1 ((uint)0x00000000)
218 #define SCC_GSMRL_RENC_DFMAN ((uint)0x00003000)
219 #define SCC_GSMRL_RENC_MANCH ((uint)0x00002000)
220 #define SCC_GSMRL_RENC_FM0 ((uint)0x00001000)
221 #define SCC_GSMRL_RENC_NRZI ((uint)0x00000800)
222 #define SCC_GSMRL_RENC_NRZ ((uint)0x00000000)
223 #define SCC_GSMRL_TENC_DFMAN ((uint)0x00000600)
224 #define SCC_GSMRL_TENC_MANCH ((uint)0x00000400)
225 #define SCC_GSMRL_TENC_FM0 ((uint)0x00000200)
226 #define SCC_GSMRL_TENC_NRZI ((uint)0x00000100)
227 #define SCC_GSMRL_TENC_NRZ ((uint)0x00000000)
228 #define SCC_GSMRL_DIAG_LE ((uint)0x000000c0) /* Loop and echo */
229 #define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080)
230 #define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040)
231 #define SCC_GSMRL_DIAG_NORM ((uint)0x00000000)
232 #define SCC_GSMRL_ENR ((uint)0x00000020)
233 #define SCC_GSMRL_ENT ((uint)0x00000010)
234 #define SCC_GSMRL_MODE_ENET ((uint)0x0000000c)
235 #define SCC_GSMRL_MODE_DDCMP ((uint)0x00000009)
236 #define SCC_GSMRL_MODE_BISYNC ((uint)0x00000008)
237 #define SCC_GSMRL_MODE_V14 ((uint)0x00000007)
238 #define SCC_GSMRL_MODE_AHDLC ((uint)0x00000006)
239 #define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005)
240 #define SCC_GSMRL_MODE_UART ((uint)0x00000004)
241 #define SCC_GSMRL_MODE_SS7 ((uint)0x00000003)
242 #define SCC_GSMRL_MODE_ATALK ((uint)0x00000002)
243 #define SCC_GSMRL_MODE_HDLC ((uint)0x00000000)
245 #define SCC_TODR_TOD ((ushort)0x8000)
249 #define SCCM_TXE ((unsigned char)0x10)
250 #define SCCM_BSY ((unsigned char)0x04)
251 #define SCCM_TX ((unsigned char)0x02)
252 #define SCCM_RX ((unsigned char)0x01)
297 uint sen_tbuf0data0; /* Save area 0 - current frame */
309 uint sen_tbuf1data0; /* Save area 0 - current frame */
332 #define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */
333 #define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */
334 #define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */
335 #define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */
336 #define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */
337 #define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */
341 #define SCC_PSMR_HBC ((ushort)0x8000) /* Enable heartbeat */
342 #define SCC_PSMR_FC ((ushort)0x4000) /* Force collision */
343 #define SCC_PSMR_RSH ((ushort)0x2000) /* Receive short frames */
344 #define SCC_PSMR_IAM ((ushort)0x1000) /* Check individual hash */
345 #define SCC_PSMR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */
346 #define SCC_PSMR_PRO ((ushort)0x0200) /* Promiscuous mode */
347 #define SCC_PSMR_BRO ((ushort)0x0100) /* Catch broadcast pkts */
348 #define SCC_PSMR_SBT ((ushort)0x0080) /* Special backoff timer */
349 #define SCC_PSMR_LPB ((ushort)0x0040) /* Set Loopback mode */
350 #define SCC_PSMR_SIP ((ushort)0x0020) /* Sample Input Pins */
351 #define SCC_PSMR_LCW ((ushort)0x0010) /* Late collision window */
352 #define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */
353 #define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */
358 #define BD_ENET_RX_EMPTY ((ushort)0x8000)
359 #define BD_ENET_RX_WRAP ((ushort)0x2000)
360 #define BD_ENET_RX_INTR ((ushort)0x1000)
361 #define BD_ENET_RX_LAST ((ushort)0x0800)
362 #define BD_ENET_RX_FIRST ((ushort)0x0400)
363 #define BD_ENET_RX_MISS ((ushort)0x0100)
364 #define BD_ENET_RX_BC ((ushort)0x0080) /* FCC Only */
365 #define BD_ENET_RX_MC ((ushort)0x0040) /* FCC Only */
366 #define BD_ENET_RX_LG ((ushort)0x0020)
367 #define BD_ENET_RX_NO ((ushort)0x0010)
368 #define BD_ENET_RX_SH ((ushort)0x0008)
369 #define BD_ENET_RX_CR ((ushort)0x0004)
370 #define BD_ENET_RX_OV ((ushort)0x0002)
371 #define BD_ENET_RX_CL ((ushort)0x0001)
372 #define BD_ENET_RX_STATS ((ushort)0x01ff) /* All status bits */
377 #define BD_ENET_TX_READY ((ushort)0x8000)
378 #define BD_ENET_TX_PAD ((ushort)0x4000)
379 #define BD_ENET_TX_WRAP ((ushort)0x2000)
380 #define BD_ENET_TX_INTR ((ushort)0x1000)
381 #define BD_ENET_TX_LAST ((ushort)0x0800)
382 #define BD_ENET_TX_TC ((ushort)0x0400)
383 #define BD_ENET_TX_DEF ((ushort)0x0200)
384 #define BD_ENET_TX_HB ((ushort)0x0100)
385 #define BD_ENET_TX_LC ((ushort)0x0080)
386 #define BD_ENET_TX_RL ((ushort)0x0040)
387 #define BD_ENET_TX_RCMASK ((ushort)0x003c)
388 #define BD_ENET_TX_UN ((ushort)0x0002)
389 #define BD_ENET_TX_CSL ((ushort)0x0001)
390 #define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */
425 #define UART_SCCM_GLR ((ushort)0x1000)
426 #define UART_SCCM_GLT ((ushort)0x0800)
427 #define UART_SCCM_AB ((ushort)0x0200)
428 #define UART_SCCM_IDL ((ushort)0x0100)
429 #define UART_SCCM_GRA ((ushort)0x0080)
430 #define UART_SCCM_BRKE ((ushort)0x0040)
431 #define UART_SCCM_BRKS ((ushort)0x0020)
432 #define UART_SCCM_CCR ((ushort)0x0008)
433 #define UART_SCCM_BSY ((ushort)0x0004)
434 #define UART_SCCM_TX ((ushort)0x0002)
435 #define UART_SCCM_RX ((ushort)0x0001)
439 #define SCU_PSMR_FLC ((ushort)0x8000)
440 #define SCU_PSMR_SL ((ushort)0x4000)
441 #define SCU_PSMR_CL ((ushort)0x3000)
442 #define SCU_PSMR_UM ((ushort)0x0c00)
443 #define SCU_PSMR_FRZ ((ushort)0x0200)
444 #define SCU_PSMR_RZS ((ushort)0x0100)
445 #define SCU_PSMR_SYN ((ushort)0x0080)
446 #define SCU_PSMR_DRT ((ushort)0x0040)
447 #define SCU_PSMR_PEN ((ushort)0x0010)
448 #define SCU_PSMR_RPM ((ushort)0x000c)
449 #define SCU_PSMR_REVP ((ushort)0x0008)
450 #define SCU_PSMR_TPM ((ushort)0x0003)
451 #define SCU_PSMR_TEVP ((ushort)0x0003)
461 #define BD_SCC_TX_LAST ((ushort)0x0800)
465 #define FCC_GFMR_DIAG_NORM ((uint)0x00000000)
466 #define FCC_GFMR_DIAG_LE ((uint)0x40000000)
467 #define FCC_GFMR_DIAG_AE ((uint)0x80000000)
468 #define FCC_GFMR_DIAG_ALE ((uint)0xc0000000)
469 #define FCC_GFMR_TCI ((uint)0x20000000)
470 #define FCC_GFMR_TRX ((uint)0x10000000)
471 #define FCC_GFMR_TTX ((uint)0x08000000)
472 #define FCC_GFMR_TTX ((uint)0x08000000)
473 #define FCC_GFMR_CDP ((uint)0x04000000)
474 #define FCC_GFMR_CTSP ((uint)0x02000000)
475 #define FCC_GFMR_CDS ((uint)0x01000000)
476 #define FCC_GFMR_CTSS ((uint)0x00800000)
477 #define FCC_GFMR_SYNL_NONE ((uint)0x00000000)
478 #define FCC_GFMR_SYNL_AUTO ((uint)0x00004000)
479 #define FCC_GFMR_SYNL_8 ((uint)0x00008000)
480 #define FCC_GFMR_SYNL_16 ((uint)0x0000c000)
481 #define FCC_GFMR_RTSM ((uint)0x00002000)
482 #define FCC_GFMR_RENC_NRZ ((uint)0x00000000)
483 #define FCC_GFMR_RENC_NRZI ((uint)0x00000800)
484 #define FCC_GFMR_REVD ((uint)0x00000400)
485 #define FCC_GFMR_TENC_NRZ ((uint)0x00000000)
486 #define FCC_GFMR_TENC_NRZI ((uint)0x00000100)
487 #define FCC_GFMR_TCRC_16 ((uint)0x00000000)
488 #define FCC_GFMR_TCRC_32 ((uint)0x00000080)
489 #define FCC_GFMR_ENR ((uint)0x00000020)
490 #define FCC_GFMR_ENT ((uint)0x00000010)
491 #define FCC_GFMR_MODE_ENET ((uint)0x0000000c)
492 #define FCC_GFMR_MODE_ATM ((uint)0x0000000a)
493 #define FCC_GFMR_MODE_HDLC ((uint)0x00000000)
584 #define FCC_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */
585 #define FCC_ENET_RXC ((ushort)0x0040) /* Control Frame Received */
586 #define FCC_ENET_TXC ((ushort)0x0020) /* Out of seq. Tx sent */
587 #define FCC_ENET_TXE ((ushort)0x0010) /* Transmit Error */
588 #define FCC_ENET_RXF ((ushort)0x0008) /* Full frame received */
589 #define FCC_ENET_BSY ((ushort)0x0004) /* Busy. Rx Frame dropped */
590 #define FCC_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */
591 #define FCC_ENET_RXB ((ushort)0x0001) /* A buffer was received */
595 #define FCC_PSMR_HBC ((uint)0x80000000) /* Enable heartbeat */
596 #define FCC_PSMR_FC ((uint)0x40000000) /* Force Collision */
597 #define FCC_PSMR_SBT ((uint)0x20000000) /* Stop backoff timer */
598 #define FCC_PSMR_LPB ((uint)0x10000000) /* Local protect. 1 = FDX */
599 #define FCC_PSMR_LCW ((uint)0x08000000) /* Late collision select */
600 #define FCC_PSMR_FDE ((uint)0x04000000) /* Full Duplex Enable */
601 #define FCC_PSMR_MON ((uint)0x02000000) /* RMON Enable */
602 #define FCC_PSMR_PRO ((uint)0x00400000) /* Promiscuous Enable */
603 #define FCC_PSMR_FCE ((uint)0x00200000) /* Flow Control Enable */
604 #define FCC_PSMR_RSH ((uint)0x00100000) /* Receive Short Frames */
605 #define FCC_PSMR_CAM ((uint)0x00000400) /* CAM enable */
606 #define FCC_PSMR_BRO ((uint)0x00000200) /* Broadcast pkt discard */
607 #define FCC_PSMR_ENCRC ((uint)0x00000080) /* Use 32-bit CRC */
653 #define SPMODE_LOOP ((ushort)0x4000) /* Loopback */
654 #define SPMODE_CI ((ushort)0x2000) /* Clock Invert */
655 #define SPMODE_CP ((ushort)0x1000) /* Clock Phase */
656 #define SPMODE_DIV16 ((ushort)0x0800) /* BRG/16 mode */
657 #define SPMODE_REV ((ushort)0x0400) /* Reversed Data */
658 #define SPMODE_MSTR ((ushort)0x0200) /* SPI Master */
659 #define SPMODE_EN ((ushort)0x0100) /* Enable */
660 #define SPMODE_LENMSK ((ushort)0x00f0) /* character length */
661 #define SPMODE_PMMSK ((ushort)0x000f) /* prescale modulus */
663 #define SPMODE_LEN(x) ((((x)-1)&0xF)<<4)
664 #define SPMODE_PM(x) ((x) &0xF)
666 #define SPI_EB ((u_char)0x10) /* big endian byte order */
668 #define BD_IIC_START ((ushort)0x0400)
673 #define CMXFCR_FC1 0x40000000 /* FCC1 connection */
674 #define CMXFCR_RF1CS_MSK 0x38000000 /* Receive FCC1 Clock Source Mask */
675 #define CMXFCR_TF1CS_MSK 0x07000000 /* Transmit FCC1 Clock Source Mask */
676 #define CMXFCR_FC2 0x00400000 /* FCC2 connection */
677 #define CMXFCR_RF2CS_MSK 0x00380000 /* Receive FCC2 Clock Source Mask */
678 #define CMXFCR_TF2CS_MSK 0x00070000 /* Transmit FCC2 Clock Source Mask */
679 #define CMXFCR_FC3 0x00004000 /* FCC3 connection */
680 #define CMXFCR_RF3CS_MSK 0x00003800 /* Receive FCC3 Clock Source Mask */
681 #define CMXFCR_TF3CS_MSK 0x00000700 /* Transmit FCC3 Clock Source Mask */
683 #define CMXFCR_RF1CS_BRG5 0x00000000 /* Receive FCC1 Clock Source is BRG5 */
684 #define CMXFCR_RF1CS_BRG6 0x08000000 /* Receive FCC1 Clock Source is BRG6 */
685 #define CMXFCR_RF1CS_BRG7 0x10000000 /* Receive FCC1 Clock Source is BRG7 */
686 #define CMXFCR_RF1CS_BRG8 0x18000000 /* Receive FCC1 Clock Source is BRG8 */
687 #define CMXFCR_RF1CS_CLK9 0x20000000 /* Receive FCC1 Clock Source is CLK9 */
688 #define CMXFCR_RF1CS_CLK10 0x28000000 /* Receive FCC1 Clock Source is CLK10 */
689 #define CMXFCR_RF1CS_CLK11 0x30000000 /* Receive FCC1 Clock Source is CLK11 */
690 #define CMXFCR_RF1CS_CLK12 0x38000000 /* Receive FCC1 Clock Source is CLK12 */
692 #define CMXFCR_TF1CS_BRG5 0x00000000 /* Transmit FCC1 Clock Source is BRG5 */
693 #define CMXFCR_TF1CS_BRG6 0x01000000 /* Transmit FCC1 Clock Source is BRG6 */
694 #define CMXFCR_TF1CS_BRG7 0x02000000 /* Transmit FCC1 Clock Source is BRG7 */
695 #define CMXFCR_TF1CS_BRG8 0x03000000 /* Transmit FCC1 Clock Source is BRG8 */
696 #define CMXFCR_TF1CS_CLK9 0x04000000 /* Transmit FCC1 Clock Source is CLK9 */
697 #define CMXFCR_TF1CS_CLK10 0x05000000 /* Transmit FCC1 Clock Source is CLK10 */
698 #define CMXFCR_TF1CS_CLK11 0x06000000 /* Transmit FCC1 Clock Source is CLK11 */
699 #define CMXFCR_TF1CS_CLK12 0x07000000 /* Transmit FCC1 Clock Source is CLK12 */
701 #define CMXFCR_RF2CS_BRG5 0x00000000 /* Receive FCC2 Clock Source is BRG5 */
702 #define CMXFCR_RF2CS_BRG6 0x00080000 /* Receive FCC2 Clock Source is BRG6 */
703 #define CMXFCR_RF2CS_BRG7 0x00100000 /* Receive FCC2 Clock Source is BRG7 */
704 #define CMXFCR_RF2CS_BRG8 0x00180000 /* Receive FCC2 Clock Source is BRG8 */
705 #define CMXFCR_RF2CS_CLK13 0x00200000 /* Receive FCC2 Clock Source is CLK13 */
706 #define CMXFCR_RF2CS_CLK14 0x00280000 /* Receive FCC2 Clock Source is CLK14 */
707 #define CMXFCR_RF2CS_CLK15 0x00300000 /* Receive FCC2 Clock Source is CLK15 */
708 #define CMXFCR_RF2CS_CLK16 0x00380000 /* Receive FCC2 Clock Source is CLK16 */
710 #define CMXFCR_TF2CS_BRG5 0x00000000 /* Transmit FCC2 Clock Source is BRG5 */
711 #define CMXFCR_TF2CS_BRG6 0x00010000 /* Transmit FCC2 Clock Source is BRG6 */
712 #define CMXFCR_TF2CS_BRG7 0x00020000 /* Transmit FCC2 Clock Source is BRG7 */
713 #define CMXFCR_TF2CS_BRG8 0x00030000 /* Transmit FCC2 Clock Source is BRG8 */
714 #define CMXFCR_TF2CS_CLK13 0x00040000 /* Transmit FCC2 Clock Source is CLK13 */
715 #define CMXFCR_TF2CS_CLK14 0x00050000 /* Transmit FCC2 Clock Source is CLK14 */
716 #define CMXFCR_TF2CS_CLK15 0x00060000 /* Transmit FCC2 Clock Source is CLK15 */
717 #define CMXFCR_TF2CS_CLK16 0x00070000 /* Transmit FCC2 Clock Source is CLK16 */
719 #define CMXFCR_RF3CS_BRG5 0x00000000 /* Receive FCC3 Clock Source is BRG5 */
720 #define CMXFCR_RF3CS_BRG6 0x00000800 /* Receive FCC3 Clock Source is BRG6 */
721 #define CMXFCR_RF3CS_BRG7 0x00001000 /* Receive FCC3 Clock Source is BRG7 */
722 #define CMXFCR_RF3CS_BRG8 0x00001800 /* Receive FCC3 Clock Source is BRG8 */
723 #define CMXFCR_RF3CS_CLK13 0x00002000 /* Receive FCC3 Clock Source is CLK13 */
724 #define CMXFCR_RF3CS_CLK14 0x00002800 /* Receive FCC3 Clock Source is CLK14 */
725 #define CMXFCR_RF3CS_CLK15 0x00003000 /* Receive FCC3 Clock Source is CLK15 */
726 #define CMXFCR_RF3CS_CLK16 0x00003800 /* Receive FCC3 Clock Source is CLK16 */
728 #define CMXFCR_TF3CS_BRG5 0x00000000 /* Transmit FCC3 Clock Source is BRG5 */
729 #define CMXFCR_TF3CS_BRG6 0x00000100 /* Transmit FCC3 Clock Source is BRG6 */
730 #define CMXFCR_TF3CS_BRG7 0x00000200 /* Transmit FCC3 Clock Source is BRG7 */
731 #define CMXFCR_TF3CS_BRG8 0x00000300 /* Transmit FCC3 Clock Source is BRG8 */
732 #define CMXFCR_TF3CS_CLK13 0x00000400 /* Transmit FCC3 Clock Source is CLK13 */
733 #define CMXFCR_TF3CS_CLK14 0x00000500 /* Transmit FCC3 Clock Source is CLK14 */
734 #define CMXFCR_TF3CS_CLK15 0x00000600 /* Transmit FCC3 Clock Source is CLK15 */
735 #define CMXFCR_TF3CS_CLK16 0x00000700 /* Transmit FCC3 Clock Source is CLK16 */
740 #define CMXSCR_GR1 0x80000000 /* Grant Support of SCC1 */
741 #define CMXSCR_SC1 0x40000000 /* SCC1 connection */
742 #define CMXSCR_RS1CS_MSK 0x38000000 /* Receive SCC1 Clock Source Mask */
743 #define CMXSCR_TS1CS_MSK 0x07000000 /* Transmit SCC1 Clock Source Mask */
744 #define CMXSCR_GR2 0x00800000 /* Grant Support of SCC2 */
745 #define CMXSCR_SC2 0x00400000 /* SCC2 connection */
746 #define CMXSCR_RS2CS_MSK 0x00380000 /* Receive SCC2 Clock Source Mask */
747 #define CMXSCR_TS2CS_MSK 0x00070000 /* Transmit SCC2 Clock Source Mask */
748 #define CMXSCR_GR3 0x00008000 /* Grant Support of SCC3 */
749 #define CMXSCR_SC3 0x00004000 /* SCC3 connection */
750 #define CMXSCR_RS3CS_MSK 0x00003800 /* Receive SCC3 Clock Source Mask */
751 #define CMXSCR_TS3CS_MSK 0x00000700 /* Transmit SCC3 Clock Source Mask */
752 #define CMXSCR_GR4 0x00000080 /* Grant Support of SCC4 */
753 #define CMXSCR_SC4 0x00000040 /* SCC4 connection */
754 #define CMXSCR_RS4CS_MSK 0x00000038 /* Receive SCC4 Clock Source Mask */
755 #define CMXSCR_TS4CS_MSK 0x00000007 /* Transmit SCC4 Clock Source Mask */
757 #define CMXSCR_RS1CS_BRG1 0x00000000 /* SCC1 Rx Clock Source is BRG1 */
758 #define CMXSCR_RS1CS_BRG2 0x08000000 /* SCC1 Rx Clock Source is BRG2 */
759 #define CMXSCR_RS1CS_BRG3 0x10000000 /* SCC1 Rx Clock Source is BRG3 */
760 #define CMXSCR_RS1CS_BRG4 0x18000000 /* SCC1 Rx Clock Source is BRG4 */
761 #define CMXSCR_RS1CS_CLK11 0x20000000 /* SCC1 Rx Clock Source is CLK11 */
762 #define CMXSCR_RS1CS_CLK12 0x28000000 /* SCC1 Rx Clock Source is CLK12 */
763 #define CMXSCR_RS1CS_CLK3 0x30000000 /* SCC1 Rx Clock Source is CLK3 */
764 #define CMXSCR_RS1CS_CLK4 0x38000000 /* SCC1 Rx Clock Source is CLK4 */
766 #define CMXSCR_TS1CS_BRG1 0x00000000 /* SCC1 Tx Clock Source is BRG1 */
767 #define CMXSCR_TS1CS_BRG2 0x01000000 /* SCC1 Tx Clock Source is BRG2 */
768 #define CMXSCR_TS1CS_BRG3 0x02000000 /* SCC1 Tx Clock Source is BRG3 */
769 #define CMXSCR_TS1CS_BRG4 0x03000000 /* SCC1 Tx Clock Source is BRG4 */
770 #define CMXSCR_TS1CS_CLK11 0x04000000 /* SCC1 Tx Clock Source is CLK11 */
771 #define CMXSCR_TS1CS_CLK12 0x05000000 /* SCC1 Tx Clock Source is CLK12 */
772 #define CMXSCR_TS1CS_CLK3 0x06000000 /* SCC1 Tx Clock Source is CLK3 */
773 #define CMXSCR_TS1CS_CLK4 0x07000000 /* SCC1 Tx Clock Source is CLK4 */
775 #define CMXSCR_RS2CS_BRG1 0x00000000 /* SCC2 Rx Clock Source is BRG1 */
776 #define CMXSCR_RS2CS_BRG2 0x00080000 /* SCC2 Rx Clock Source is BRG2 */
777 #define CMXSCR_RS2CS_BRG3 0x00100000 /* SCC2 Rx Clock Source is BRG3 */
778 #define CMXSCR_RS2CS_BRG4 0x00180000 /* SCC2 Rx Clock Source is BRG4 */
779 #define CMXSCR_RS2CS_CLK11 0x00200000 /* SCC2 Rx Clock Source is CLK11 */
780 #define CMXSCR_RS2CS_CLK12 0x00280000 /* SCC2 Rx Clock Source is CLK12 */
781 #define CMXSCR_RS2CS_CLK3 0x00300000 /* SCC2 Rx Clock Source is CLK3 */
782 #define CMXSCR_RS2CS_CLK4 0x00380000 /* SCC2 Rx Clock Source is CLK4 */
784 #define CMXSCR_TS2CS_BRG1 0x00000000 /* SCC2 Tx Clock Source is BRG1 */
785 #define CMXSCR_TS2CS_BRG2 0x00010000 /* SCC2 Tx Clock Source is BRG2 */
786 #define CMXSCR_TS2CS_BRG3 0x00020000 /* SCC2 Tx Clock Source is BRG3 */
787 #define CMXSCR_TS2CS_BRG4 0x00030000 /* SCC2 Tx Clock Source is BRG4 */
788 #define CMXSCR_TS2CS_CLK11 0x00040000 /* SCC2 Tx Clock Source is CLK11 */
789 #define CMXSCR_TS2CS_CLK12 0x00050000 /* SCC2 Tx Clock Source is CLK12 */
790 #define CMXSCR_TS2CS_CLK3 0x00060000 /* SCC2 Tx Clock Source is CLK3 */
791 #define CMXSCR_TS2CS_CLK4 0x00070000 /* SCC2 Tx Clock Source is CLK4 */
793 #define CMXSCR_RS3CS_BRG1 0x00000000 /* SCC3 Rx Clock Source is BRG1 */
794 #define CMXSCR_RS3CS_BRG2 0x00000800 /* SCC3 Rx Clock Source is BRG2 */
795 #define CMXSCR_RS3CS_BRG3 0x00001000 /* SCC3 Rx Clock Source is BRG3 */
796 #define CMXSCR_RS3CS_BRG4 0x00001800 /* SCC3 Rx Clock Source is BRG4 */
797 #define CMXSCR_RS3CS_CLK5 0x00002000 /* SCC3 Rx Clock Source is CLK5 */
798 #define CMXSCR_RS3CS_CLK6 0x00002800 /* SCC3 Rx Clock Source is CLK6 */
799 #define CMXSCR_RS3CS_CLK7 0x00003000 /* SCC3 Rx Clock Source is CLK7 */
800 #define CMXSCR_RS3CS_CLK8 0x00003800 /* SCC3 Rx Clock Source is CLK8 */
802 #define CMXSCR_TS3CS_BRG1 0x00000000 /* SCC3 Tx Clock Source is BRG1 */
803 #define CMXSCR_TS3CS_BRG2 0x00000100 /* SCC3 Tx Clock Source is BRG2 */
804 #define CMXSCR_TS3CS_BRG3 0x00000200 /* SCC3 Tx Clock Source is BRG3 */
805 #define CMXSCR_TS3CS_BRG4 0x00000300 /* SCC3 Tx Clock Source is BRG4 */
806 #define CMXSCR_TS3CS_CLK5 0x00000400 /* SCC3 Tx Clock Source is CLK5 */
807 #define CMXSCR_TS3CS_CLK6 0x00000500 /* SCC3 Tx Clock Source is CLK6 */
808 #define CMXSCR_TS3CS_CLK7 0x00000600 /* SCC3 Tx Clock Source is CLK7 */
809 #define CMXSCR_TS3CS_CLK8 0x00000700 /* SCC3 Tx Clock Source is CLK8 */
811 #define CMXSCR_RS4CS_BRG1 0x00000000 /* SCC4 Rx Clock Source is BRG1 */
812 #define CMXSCR_RS4CS_BRG2 0x00000008 /* SCC4 Rx Clock Source is BRG2 */
813 #define CMXSCR_RS4CS_BRG3 0x00000010 /* SCC4 Rx Clock Source is BRG3 */
814 #define CMXSCR_RS4CS_BRG4 0x00000018 /* SCC4 Rx Clock Source is BRG4 */
815 #define CMXSCR_RS4CS_CLK5 0x00000020 /* SCC4 Rx Clock Source is CLK5 */
816 #define CMXSCR_RS4CS_CLK6 0x00000028 /* SCC4 Rx Clock Source is CLK6 */
817 #define CMXSCR_RS4CS_CLK7 0x00000030 /* SCC4 Rx Clock Source is CLK7 */
818 #define CMXSCR_RS4CS_CLK8 0x00000038 /* SCC4 Rx Clock Source is CLK8 */
820 #define CMXSCR_TS4CS_BRG1 0x00000000 /* SCC4 Tx Clock Source is BRG1 */
821 #define CMXSCR_TS4CS_BRG2 0x00000001 /* SCC4 Tx Clock Source is BRG2 */
822 #define CMXSCR_TS4CS_BRG3 0x00000002 /* SCC4 Tx Clock Source is BRG3 */
823 #define CMXSCR_TS4CS_BRG4 0x00000003 /* SCC4 Tx Clock Source is BRG4 */
824 #define CMXSCR_TS4CS_CLK5 0x00000004 /* SCC4 Tx Clock Source is CLK5 */
825 #define CMXSCR_TS4CS_CLK6 0x00000005 /* SCC4 Tx Clock Source is CLK6 */
826 #define CMXSCR_TS4CS_CLK7 0x00000006 /* SCC4 Tx Clock Source is CLK7 */
827 #define CMXSCR_TS4CS_CLK8 0x00000007 /* SCC4 Tx Clock Source is CLK8 */