Lines Matching refs:r3
31 lis r3, HID0_EMCP@h /* enable machine check */
33 ori r3,r3,HID0_TBEN@l /* enable Timebase */
36 ori r3,r3,HID0_ENMAS7@l /* enable MAS7 updates */
38 mtspr SPRN_HID0,r3
41 li r3,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */
47 ori r3, r3, HID1_MBDD@l
49 mtspr SPRN_HID1,r3
53 mfspr r3,SPRN_HDBCR1
54 oris r3,r3,0x0100
55 mtspr SPRN_HDBCR1,r3
59 mfspr r3,SPRN_SVR
60 rlwinm r3,r3,0,0xff
62 cmpw r3,r4
67 cmpw r3,r4
77 mfspr r3,SPRN_HDBCR0
79 rlwimi r3,r4,0,0x1f8
80 mtspr SPRN_HDBCR0,r3
86 lis r3,BUCSR_ENABLE@h
87 ori r3,r3,BUCSR_ENABLE@l
88 mtspr SPRN_BUCSR,r3
91 li r3,0
92 mttbl r3
93 mttbu r3
100 mfspr r3,SPRN_L1CSR1
101 and. r1,r3,r2
104 lis r3,(L1CSR1_CPE|L1CSR1_ICE)@h
105 ori r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l
106 mtspr SPRN_L1CSR1,r3
109 mfspr r3,SPRN_L1CSR1
110 andi. r1,r3,L1CSR1_ICE@l
118 mfspr r3,SPRN_L1CSR0
119 and. r1,r3,r2
122 lis r3,(L1CSR0_CPE|L1CSR0_DCE)@h
123 ori r3,r3,(L1CSR0_CPE|L1CSR0_DCE)@l
124 mtspr SPRN_L1CSR0,r3
127 mfspr r3,SPRN_L1CSR0
128 andi. r1,r3,L1CSR0_DCE@l
134 lis r3,toreset(__spin_table_addr)@h
135 ori r3,r3,toreset(__spin_table_addr)@l
136 lwz r3,0(r3)
183 add r10,r3,r8
201 mfspr r3,SPRN_SVR
202 rlwinm r6,r3,24,~0x800 /* clear E bit */
209 rlwinm r3,r3,0,0xf0
211 cmpw r3,r5
215 lis r3,toreset(enable_cpu_a011_workaround)@ha
216 lwz r3,toreset(enable_cpu_a011_workaround)@l(r3)
217 cmpwi r3,0
220 mfspr r3,L1CSR2
221 oris r3,r3,(L1CSR2_DCWS)@h
222 mtspr L1CSR2,r3
232 mfspr r3,L1CSR2
233 andis. r3,r3,(L1CSR2_DCWS)@h
235 mfspr r3, SPRN_HDBCR0
236 oris r3, r3, 0x8000
237 mtspr SPRN_HDBCR0, r3
243 mfspr r3,SPRN_SVR
244 rlwinm r6,r3,24,~0x800 /* clear E bit of SVR */
246 lis r3,SVR_P2040@h
247 ori r3,r3,SVR_P2040@l
248 cmpw r6,r3
257 mfspr r3,SPRN_L2CSR0
258 and. r1,r3,r2
263 addi r3,r8,1
264 mtspr SPRN_L2CSR1,r3
267 lis r3,CONFIG_SYS_INIT_L2CSR0@h
268 ori r3,r3,CONFIG_SYS_INIT_L2CSR0@l
269 mtspr SPRN_L2CSR0,r3
272 mfspr r3,SPRN_L2CSR0
273 andis. r1,r3,L2CSR0_L2E@h
348 lis r3,(spin_table_compat - __second_half_boot_page)@h
349 ori r3,r3,(spin_table_compat - __second_half_boot_page)@l
350 add r3,r3,r11 /* r11 has the address of __second_half_boot_page */
351 lwz r14,0(r3)
373 li r3,0
376 stw r3,ENTRY_ADDR_UPPER(r10)
377 stw r3,ENTRY_R3_UPPER(r10)
379 stw r3,ENTRY_RESV(r10)
427 ld r3,ENTRY_R3_UPPER(r10)
429 lwz r3,ENTRY_R3_LOWER(r10)