Lines Matching +full:spin +full:- +full:table
2 * Copyright 2008-2012 Freescale Semiconductor, Inc.
5 * SPDX-License-Identifier: GPL-2.0+
8 #include <asm-offsets.h>
95 /* Enable/invalidate the I-Cache */
113 /* Enable/invalidate the D-Cache */
131 #define toreset(x) (x - __secondary_start_page + 0xfffff000)
133 /* get our PIR to figure out our table entry */
142 * 0-17 Reserved (logic 0s)
143 * 18-19 CHIP_ID, 2'b00 - SoC 1
144 * all others - reserved
145 * 20-24 CLUSTER_ID 5'b00000 - CCM 1
146 * all others - reserved
147 * 25-26 CORE_CLUSTER_ID 2'b00 - cluster 1
148 * 2'b01 - cluster 2
149 * 2'b10 - cluster 3
150 * 2'b11 - cluster 4
151 * 27-28 CORE_ID 2'b00 - core 0
152 * 2'b01 - core 1
153 * 2'b10 - core 2
154 * 2'b11 - core 3
155 * 29-31 THREAD_ID 3'b000 - thread 0
156 * 3'b001 - thread 1
158 * Power-on PIR increments threads by 0x01, cores within a cluster by 0x08
168 add r5,r5,r8 /* for spin table index */
182 slwi r8,r5,6 /* spin table is padded to 64 byte */
228 * A-005812 workaround sets bit 32 of SPR 976 for SoCs running in
277 /* setup mapping for the spin table, WIMGE=0b00100 */
338 .space 4092 - (__secondary_start_code_end - __secondary_start_page)
343 /* this is a separated page for the spin table and cacheable boot code */
348 lis r3,(spin_table_compat - __second_half_boot_page)@h
349 ori r3,r3,(spin_table_compat - __second_half_boot_page)@l
363 * r10 has the base address of the spin table.
364 * spin table is defined as
384 /* spin waiting for addr */
387 * To comply with ePAPR 1.1, the spin table has been moved to cache-enabled
389 * accepted for Linux kernel. Other OS needs similar fix to spin table.
390 * For OSes with old spin table code, we can enable this temporary fix by
423 * entry. The high 32-bits are ignored on 32-bit chip implementations.
424 * 64-bit chip implementations however shall load all 64-bits
447 * which maps 0xfffff000-0xffffffff one-to-one. We set up a
486 .space 4096 - (__spin_table_end - __spin_table)