Lines Matching +full:0 +full:x08020000

15 #define GUTS_PORDEVSR_OFFS		0xc
16 #define GUTS_PORDEVSR_SERDES2_IO_SEL	0x38000000
20 #define	FSL_SRDSCR0_OFFS	0x0
21 #define FSL_SRDSCR0_TXEQA_MASK	0x00007000
22 #define FSL_SRDSCR0_TXEQA_SGMII	0x00004000
23 #define FSL_SRDSCR0_TXEQA_SATA	0x00001000
24 #define FSL_SRDSCR0_TXEQE_MASK	0x00000700
25 #define FSL_SRDSCR0_TXEQE_SGMII	0x00000400
26 #define FSL_SRDSCR0_TXEQE_SATA	0x00000100
29 #define FSL_SRDSCR1_OFFS	0x4
30 #define FSL_SRDSCR1_LANEA_MASK	0x80200000
31 #define FSL_SRDSCR1_LANEA_OFF	0x80200000
32 #define FSL_SRDSCR1_LANEE_MASK	0x08020000
33 #define FSL_SRDSCR1_LANEE_OFF	0x08020000
36 #define FSL_SRDSCR2_OFFS	0x8
37 #define FSL_SRDSCR2_EICA_MASK	0x00001f00
38 #define FSL_SRDSCR2_EICA_SGMII	0x00000400
39 #define FSL_SRDSCR2_EICA_SATA	0x00001400
40 #define FSL_SRDSCR2_EICE_MASK	0x0000001f
41 #define FSL_SRDSCR2_EICE_SGMII	0x00000004
42 #define FSL_SRDSCR2_EICE_SATA	0x00000014
45 #define FSL_SRDSCR3_OFFS	0xc
46 #define FSL_SRDSCR3_LANEA_MASK	0x3f000700
47 #define FSL_SRDSCR3_LANEA_SGMII	0x00000000
48 #define FSL_SRDSCR3_LANEA_SATA	0x15000500
49 #define FSL_SRDSCR3_LANEE_MASK	0x003f0007
50 #define FSL_SRDSCR3_LANEE_SGMII	0x00000000
51 #define FSL_SRDSCR3_LANEE_SATA	0x00150005
59 	[0x2] = {PCIE1, PCIE1, PCIE1, PCIE1, NONE, NONE, NONE, NONE},
60 	[0x3] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1},
61 	[0x5] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2},
62 	[0x7] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE3, PCIE3},
66 	[0x1] = {SATA1, SATA2},
67 	[0x3] = {SATA1, NONE},
68 	[0x4] = {SGMII_TSEC1, SGMII_TSEC3},
69 	[0x6] = {SGMII_TSEC1, NONE},
115 		/* CR 0 */  in fsl_serdes_init()
143 		/* CR 0 */  in fsl_serdes_init()
165 		/* CR 0 */  in fsl_serdes_init()
193 		/* CR 0 */  in fsl_serdes_init()
231 	for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {  in fsl_serdes_init()
244 	for (lane = 0; lane < SRDS2_MAX_LANES; lane++) {  in fsl_serdes_init()