Lines Matching +full:cpu +full:- +full:nr
2 * Copyright 2008-2011 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
28 * Determine if U-Boot should keep secondary cores in reset, or let them out
46 int cpu_reset(int nr) in cpu_reset() argument
49 out_be32(&pic->pir, 1 << nr); in cpu_reset()
51 (void)in_be32(&pic->pir); in cpu_reset()
52 out_be32(&pic->pir, 0x0); in cpu_reset()
57 int cpu_status(int nr) in cpu_status() argument
64 if (nr == id) { in cpu_status()
67 } else if (is_core_disabled(nr)) { in cpu_status()
70 table = (u32 *)&__spin_table + nr * NUM_BOOT_ENTRY; in cpu_status()
71 printf("Running on cpu %d\n", id); in cpu_status()
74 printf(" addr - 0x%08x\n", table[BOOT_ENTRY_ADDR_LOWER]); in cpu_status()
75 printf(" r3 - 0x%08x\n", table[BOOT_ENTRY_R3_LOWER]); in cpu_status()
76 printf(" pir - 0x%08x\n", table[BOOT_ENTRY_PIR]); in cpu_status()
83 int cpu_disable(int nr) in cpu_disable() argument
87 setbits_be32(&gur->coredisrl, 1 << nr); in cpu_disable()
92 int is_core_disabled(int nr) { in is_core_disabled() argument
94 u32 coredisrl = in_be32(&gur->coredisrl); in is_core_disabled()
96 return (coredisrl & (1 << nr)); in is_core_disabled()
99 int cpu_disable(int nr) in cpu_disable() argument
103 switch (nr) { in cpu_disable()
105 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_CPU0); in cpu_disable()
108 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_CPU1); in cpu_disable()
111 printf("Invalid cpu number for disable %d\n", nr); in cpu_disable()
118 int is_core_disabled(int nr) { in is_core_disabled() argument
120 u32 devdisr = in_be32(&gur->devdisr); in is_core_disabled()
122 switch (nr) { in is_core_disabled()
128 printf("Invalid cpu number for disable %d\n", nr); in is_core_disabled()
141 int cpu_release(int nr, int argc, char * const argv[]) in cpu_release() argument
143 u32 i, val, *table = (u32 *)&__spin_table + nr * NUM_BOOT_ENTRY; in cpu_release()
149 if (nr == get_my_id()) { in cpu_release()
163 if (argv[i][0] != '-') { in cpu_release()
191 bootpg = ((gd->ram_size > CONFIG_MAX_MEM_MAPPED) ? in determine_mp_bootpg()
192 CONFIG_MAX_MEM_MAPPED : gd->ram_size) + in determine_mp_bootpg()
193 CONFIG_SYS_SDRAM_BASE - 4096; in determine_mp_bootpg()
199 * Erratum A004468 has two parts. The 3-way interleaving applies to T4240, in determine_mp_bootpg()
200 * to be fixed in rev 2.0. The 2-way interleaving applies to many SoCs. But in determine_mp_bootpg()
201 * the way boot page chosen in u-boot avoids hitting this erratum. So only in determine_mp_bootpg()
202 * thw workaround for 3-way interleaving is needed. in determine_mp_bootpg()
204 * To make sure boot page translation works with 3-Way DDR interleaving in determine_mp_bootpg()
222 check--; in determine_mp_bootpg()
230 check--; in determine_mp_bootpg()
267 whoami = in_be32(&pic->whoami); in plat_mp_up()
269 out_be32(&ccm->bstrl, bootpg); in plat_mp_up()
275 out_be32(&ccm->bstrar, LAW_EN | e.trgt_id << 20 | brsize); in plat_mp_up()
279 in_be32(&ccm->bstrar); in plat_mp_up()
282 out_be32(&rcpm->ctbenrl, cpu_up_mask); in plat_mp_up()
284 out_be32(&gur->brrl, mask); in plat_mp_up()
288 unsigned int i, cpu, nr_cpus = cpu_numcores(); in plat_mp_up() local
290 for_each_cpu(i, cpu, nr_cpus, mask) { in plat_mp_up()
291 if (table[cpu * NUM_BOOT_ENTRY + BOOT_ENTRY_ADDR_LOWER]) in plat_mp_up()
292 cpu_up_mask |= (1 << cpu); in plat_mp_up()
299 timeout--; in plat_mp_up()
303 printf("CPU up timeout. CPU up mask is %x should be %x\n", in plat_mp_up()
307 out_be32(&rcpm->ctbenrl, 0); in plat_mp_up()
310 in_be32(&rcpm->ctbenrl); in plat_mp_up()
315 out_be32(&rcpm->ctbenrl, mask); in plat_mp_up()
323 * reset a processor core to put it back into U-Boot's spinloop. in plat_mp_up()
325 clrbits_be32(&ccm->bstrar, LAW_EN); in plat_mp_up()
340 whoami = in_be32(&pic->whoami); in plat_mp_up()
341 out_be32(&ecm->bptr, 0x80000000 | (bootpg >> 12)); in plat_mp_up()
344 devdisr = in_be32(&gur->devdisr); in plat_mp_up()
349 out_be32(&gur->devdisr, devdisr); in plat_mp_up()
352 up = ((1 << cpu_numcores()) - 1); in plat_mp_up()
353 bpcr = in_be32(&ecm->eebpcr); in plat_mp_up()
355 out_be32(&ecm->eebpcr, bpcr); in plat_mp_up()
371 timeout--; in plat_mp_up()
375 printf("CPU up timeout. CPU up mask is %x should be %x\n", in plat_mp_up()
383 out_be32(&gur->devdisr, devdisr); in plat_mp_up()
386 in_be32(&gur->devdisr); in plat_mp_up()
392 out_be32(&gur->devdisr, devdisr); in plat_mp_up()
400 * reset a processor core to put it back into U-Boot's spinloop. in plat_mp_up()
402 clrbits_be32(&ecm->bptr, 0x80000000); in plat_mp_up()
429 * 8K is used for the workaround of 3-way DDR interleaving in setup_mp()
442 * Store the bootpg's cache-able half address for use by secondary in setup_mp()
443 * CPU cores to continue to boot in setup_mp()
457 if (i != -1) { in setup_mp()