Lines Matching +full:de +full:- +full:asserting
2 * Copyright 2004,2007-2011 Freescale Semiconductor, Inc.
7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
9 * SPDX-License-Identifier: GPL-2.0+
62 u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC) in checkcpu()
67 u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO) in checkcpu()
91 setbits_be32(&gur->devdisr2, FSL_CORENET_DEVDISR2_DTSEC1_6 || in checkcpu()
93 setbits_be32(&gur->devdisr3, FSL_CORENET_DEVDISR3_PCIE3); in checkcpu()
94 setbits_be32(&gur->devdisr5, FSL_CORENET_DEVDISR5_DDR3); in checkcpu()
103 setbits_be32(&rcpm->pcph20setr, 0xf0); in checkcpu()
106 setbits_be32(&rcpm->clpcl10setr, 1 << 1); in checkcpu()
116 printf("CPU%d: ", pic->whoami); in checkcpu()
121 cpu = gd->arch.cpu; in checkcpu()
123 puts(cpu->name); in checkcpu()
172 printf("CPU%d:%-4s MHz, ", core, in checkcpu()
180 printf("DSP CPU%d:%-4s MHz, ", j, in checkcpu()
185 printf("\n CCB:%-4s MHz,", strmhz(buf1, sysinfo.freq_systembus)); in checkcpu()
190 printf(" DDR:%-4s MHz (%s MT/s data rate) " in checkcpu()
195 printf(" DDR:%-4s MHz (%s MT/s data rate) " in checkcpu()
203 printf(" DDR:%-4s MHz (%s MT/s data rate), ", in checkcpu()
208 printf(" DDR:%-4s MHz (%s MT/s data rate) " in checkcpu()
214 printf(" DDR:%-4s MHz (%s MT/s data rate) " in checkcpu()
224 printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freq_localbus)); in checkcpu()
232 printf("IFC:%-4s MHz\n", strmhz(buf1, sysinfo.freq_localbus)); in checkcpu()
240 printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freq_qe)); in checkcpu()
245 printf("CPRI:%-4s MHz", strmhz(buf1, sysinfo.freq_cpri)); in checkcpu()
250 printf("MAPLE:%-4s MHz, ", strmhz(buf1, sysinfo.freq_maple)); in checkcpu()
251 printf("MAPLE-ULB:%-4s MHz, ", strmhz(buf1, sysinfo.freq_maple_ulb)); in checkcpu()
252 printf("MAPLE-eTVPE:%-4s MHz\n", in checkcpu()
271 puts("L1: D-cache 32 KiB enabled\n I-cache 32 KiB enabled\n"); in checkcpu()
278 for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) { in checkcpu()
279 u32 rcw = in_be32(&gur->rcwsr[i]); in checkcpu()
292 /* ------------------------------------------------------------------------- */
303 * Make sure MSR[DE] = 1. This only resets the core. in do_reset()
315 /* Attempt board-specific reset */ in do_reset()
318 /* Next try asserting HRESET_REQ */ in do_reset()
319 out_be32(&gur->rstcr, 0x2); in do_reset()
337 return (gd->bus_clk + (tbclk_div >> 1)) / tbclk_div; in get_tbclk()
371 * Initializes on-chip MMC controllers.
401 /* Common ddr init for non-corenet fsl 85xx platforms */
409 gd->ram_size = fsl_ddr_sdram_size(); in dram_init()
411 gd->ram_size = (phys_size_t)CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; in dram_init()
430 out_be32(&gur->ddrdllcr, 0x81000000); in dram_init()
433 while (in_be32(&gur->ddrdllcr) != 0x81000100) { in dram_init()
434 setbits_be32(&gur->devdisr, 0x00010000); in dram_init()
437 clrbits_be32(&gur->devdisr, 0x00010000); in dram_init()
466 gd->ram_size = dram_size; in dram_init()
475 /* Board-specific functions defined in each board's ddr.c */
590 if (ddr_esel != -1) { in reset_tlb()
594 return -1; in reset_tlb()
608 phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED); in arch_memory_test_advance()
615 test_cap = gd->ram_size; in arch_memory_test_advance()
618 if (p_addr < test_cap - 1) { in arch_memory_test_advance()
619 p_size = min(test_cap - p_addr, CONFIG_MAX_MEM_MAPPED); in arch_memory_test_advance()
620 if (reset_tlb(p_addr, p_size, phys_offset) == -1) in arch_memory_test_advance()
621 return -1; in arch_memory_test_advance()
624 printf("Testing 0x%08llx - 0x%08llx\n", in arch_memory_test_advance()
626 (u64)(*vstart) + (*phys_offset) + (*size) - 1); in arch_memory_test_advance()
636 phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED); in arch_memory_test_prepare()
645 if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) { in arch_memory_test_prepare()
651 printf("Testing 0x%08llx - 0x%08llx\n", in arch_memory_test_prepare()
653 (u64)(*vstart) + (*phys_offset) + (*size) - 1); in arch_memory_test_prepare()
671 if (ddr_esel != -1) { in arch_memory_test_cleanup()
679 setup_ddr_tlbs(gd->ram_size>>20); in arch_memory_test_cleanup()