26 	void __iomem *dcsr = (void *)CONFIG_SYS_DCSRBAR + 0xb0000;  in check_erratum_a4849()
31 		0x50, 0x54, 0x58, 0x90, 0x94, 0x98  in check_erratum_a4849()
36 		0x60, 0x64, 0x68, 0x6c, 0xa0, 0xa4, 0xa8, 0xac  in check_erratum_a4849()
39 	uint32_t x108; /* The value that should be at offset 0x108 */  in check_erratum_a4849()  local
41 	for (i = 0; i < ARRAY_SIZE(offsets); i++) {  in check_erratum_a4849()
49 	x108 = 0x12;  in check_erratum_a4849()
54 	 * For P4080, the erratum document says that the value at offset 0x108  in check_erratum_a4849()
55 	 * should be 0x12 on rev2, or 0x1c on rev3.  in check_erratum_a4849()
58 		x108 = 0x12;  in check_erratum_a4849()
60 		x108 = 0x1c;  in check_erratum_a4849()
63 	if (in_be32(dcsr + 0x108) != x108) {  in check_erratum_a4849()
81  * 0x1B00_0001, Register 2 = 0x0088_0000, and Register 3 = 0x4000_0000.
90 	for (lane = 0; lane < SRDS_MAX_LANES; lane++) {  in check_erratum_a4580()
101 			if ((in_be32(&srds_lane->ttlcr0) != 0x1b000001) ||  in check_erratum_a4580()
102 			    (in_be32(&srds_lane->res4[1]) != 0x880000) ||  in check_erratum_a4580()
103 			    (in_be32(&srds_lane->res4[3]) != 0x40000044)) {  in check_erratum_a4580()
123 	u32 __iomem *plldgdcr = (void *)(CONFIG_SYS_DCSRBAR + 0x21c20);  in check_erratum_a007212()
125 	if (in_be32(plldgdcr) & 0x1fe) {  in check_erratum_a007212()
140 	if (IS_SVR_REV(svr, 1, 0)) {  in do_errata()
225 	if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0))  in do_errata()
232 	if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0))  in do_errata()
248 	if (IS_SVR_REV(svr, 1, 0))  in do_errata()
285 	if (IS_SVR_REV(svr, 1, 0))  in do_errata()
323 	if (IS_SVR_REV(svr, 1, 0))  in do_errata()
340 	return 0;  in do_errata()
344 	errata, 1, 0,	do_errata,