Lines Matching +full:350 +full:ps

333 		if (ddrc_clk <= 460 && ddrc_clk > 350)  in spd_sdram()
335 		else if (ddrc_clk <=350 && ddrc_clk > 280)  in spd_sdram()
342 		if (ddrc_clk <= 460 && ddrc_clk > 350) {  in spd_sdram()
343 			/* DDR controller clk at 350~460 */  in spd_sdram()
346 		} else if (ddrc_clk <= 350 && ddrc_clk > 280) {  in spd_sdram()
347 			/* DDR controller clk at 280~350 */  in spd_sdram()
373 		if (ddrc_clk <= 350 && ddrc_clk > 280) {  in spd_sdram()
374 			/* DDR controller clk at 280~350 */  in spd_sdram()
395 		if (ddrc_clk <= 350 && ddrc_clk > 280) {  in spd_sdram()
396 			/* DDR controller clk at 280~350 */  in spd_sdram()
411 		if (ddrc_clk <= 350 && ddrc_clk > 230) {  in spd_sdram()
412 			/* DDR controller clk at 230~350 */  in spd_sdram()
498 		trfc = spd.trfc * 1000;		/* up to ps */  in spd_sdram()
517 	 * Trcd, Byte 29, from quarter nanos to ps and clocks.  in spd_sdram()