45 	unsigned long end, line_size;  in invalidate_icache_all()  local
47 	end = line_size * CACHE_WAY(ICACHE) * CACHE_SET(ICACHE);  in invalidate_icache_all()
49 		end -= line_size;  in invalidate_icache_all()
50 		__asm__ volatile ("\n\tcctl %0, L1I_IX_INVAL" : : "r" (end));  in invalidate_icache_all()
52 		end -= line_size;  in invalidate_icache_all()
53 		__asm__ volatile ("\n\tcctl %0, L1I_IX_INVAL" : : "r" (end));  in invalidate_icache_all()
55 		end -= line_size;  in invalidate_icache_all()
56 		__asm__ volatile ("\n\tcctl %0, L1I_IX_INVAL" : : "r" (end));  in invalidate_icache_all()
57 		end -= line_size;  in invalidate_icache_all()
58 		__asm__ volatile ("\n\tcctl %0, L1I_IX_INVAL" : : "r" (end));  in invalidate_icache_all()
59 	} while (end > 0);  in invalidate_icache_all()
62 void invalidate_icache_range(unsigned long start, unsigned long end)  in invalidate_icache_range()  argument
67 	while (end > start) {  in invalidate_icache_range()
118 void invalidate_icache_range(unsigned long start, unsigned long end)  in invalidate_icache_range()  argument
140 	unsigned long end, line_size;  in dcache_wbinval_all()  local
142 	end = line_size * CACHE_WAY(DCACHE) * CACHE_SET(DCACHE);  in dcache_wbinval_all()
144 		end -= line_size;  in dcache_wbinval_all()
145 		__asm__ volatile ("\n\tcctl %0, L1D_IX_WB" : : "r" (end));  in dcache_wbinval_all()
146 		__asm__ volatile ("\n\tcctl %0, L1D_IX_INVAL" : : "r" (end));  in dcache_wbinval_all()
147 		end -= line_size;  in dcache_wbinval_all()
148 		__asm__ volatile ("\n\tcctl %0, L1D_IX_WB" : : "r" (end));  in dcache_wbinval_all()
149 		__asm__ volatile ("\n\tcctl %0, L1D_IX_INVAL" : : "r" (end));  in dcache_wbinval_all()
150 		end -= line_size;  in dcache_wbinval_all()
151 		__asm__ volatile ("\n\tcctl %0, L1D_IX_WB" : : "r" (end));  in dcache_wbinval_all()
152 		__asm__ volatile ("\n\tcctl %0, L1D_IX_INVAL" : : "r" (end));  in dcache_wbinval_all()
153 		end -= line_size;  in dcache_wbinval_all()
154 		__asm__ volatile ("\n\tcctl %0, L1D_IX_WB" : : "r" (end));  in dcache_wbinval_all()
155 		__asm__ volatile ("\n\tcctl %0, L1D_IX_INVAL" : : "r" (end));  in dcache_wbinval_all()
157 	} while (end > 0);  in dcache_wbinval_all()
160 void flush_dcache_range(unsigned long start, unsigned long end)  in flush_dcache_range()  argument
166 	while (end > start) {  in flush_dcache_range()
175 void invalidate_dcache_range(unsigned long start, unsigned long end)  in invalidate_dcache_range()  argument
180 	while (end > start) {  in invalidate_dcache_range()
227 void flush_dcache_range(unsigned long start, unsigned long end)  in flush_dcache_range()  argument
231 void invalidate_dcache_range(unsigned long start, unsigned long end)  in invalidate_dcache_range()  argument