20 #define ETH0_BASE AU1000_ETH0_BASE  macro
24 #define ETH0_BASE AU1100_ETH0_BASE  macro
28 #define ETH0_BASE AU1500_ETH0_BASE  macro
32 #define ETH0_BASE AU1550_ETH0_BASE  macro
79 	volatile u32 *mii_control_reg = (volatile u32*)(ETH0_BASE+MAC_MII_CNTRL);  in au1x00_miiphy_read()
80 	volatile u32 *mii_data_reg = (volatile u32*)(ETH0_BASE+MAC_MII_DATA);  in au1x00_miiphy_read()
112 	volatile u32 *mii_control_reg = (volatile u32*)(ETH0_BASE+MAC_MII_CNTRL);  in au1x00_miiphy_write()
113 	volatile u32 *mii_data_reg = (volatile u32*)(ETH0_BASE+MAC_MII_DATA);  in au1x00_miiphy_write()
211 	volatile u32 *mac_ctrl = (volatile u32*)(ETH0_BASE+MAC_CONTROL);  in au1x00_init()
212 	volatile u32 *mac_addr_high = (volatile u32*)(ETH0_BASE+MAC_ADDRESS_HIGH);  in au1x00_init()
213 	volatile u32 *mac_addr_low = (volatile u32*)(ETH0_BASE+MAC_ADDRESS_LOW);  in au1x00_init()
214 	volatile u32 *mac_mcast_high = (volatile u32*)(ETH0_BASE+MAC_MCAST_HIGH);  in au1x00_init()
215 	volatile u32 *mac_mcast_low = (volatile u32*)(ETH0_BASE+MAC_MCAST_LOW);  in au1x00_init()