Lines Matching refs:t1
103 lw t1, QCA953X_RESET_REG_RESET_MODULE(t0)
105 or t1, t1, t2
106 sw t1, QCA953X_RESET_REG_RESET_MODULE(t0)
108 lw t1, QCA953X_RESET_REG_RESET_MODULE(t0)
110 and t1, t1, t2
111 sw t1, QCA953X_RESET_REG_RESET_MODULE(t0)
116 li t1, 0x01
117 sw t1, QCA953X_RTC_REG_SYNC_RESET(t0)
123 lw t1, QCA953X_RTC_REG_SYNC_STATUS(t0)
124 andi t1, t1, 0x02
125 beqz t1, 1b
129 li t1, MK_DPLL2(2, 16)
130 sw t1, QCA953X_SRIF_BB_DPLL2_REG(t0)
131 sw t1, QCA953X_SRIF_PCIE_DPLL2_REG(t0)
132 sw t1, QCA953X_SRIF_DDR_DPLL2_REG(t0)
133 sw t1, QCA953X_SRIF_CPU_DPLL2_REG(t0)
136 lw t1, QCA953X_PLL_CLK_CTRL_REG(t0)
137 ori t1, PLL_CLK_CTRL_PLL_BYPASS
138 sw t1, QCA953X_PLL_CLK_CTRL_REG(t0)
141 li t1, PLL_CPU_CONF_VAL
142 sw t1, QCA953X_PLL_CPU_CONFIG_REG(t0)
145 li t1, PLL_DDR_CONF_VAL
146 sw t1, QCA953X_PLL_DDR_CONFIG_REG(t0)
149 li t1, PLL_CLK_CTRL_VAL
150 sw t1, QCA953X_PLL_CLK_CTRL_REG(t0)
153 lw t1, QCA953X_PLL_CPU_CONFIG_REG(t0)
155 and t1, t1, t2
156 sw t1, QCA953X_PLL_CPU_CONFIG_REG(t0)
159 lw t1, QCA953X_PLL_DDR_CONFIG_REG(t0)
161 and t1, t1, t2
162 sw t1, QCA953X_PLL_DDR_CONFIG_REG(t0)
165 lw t1, QCA953X_PLL_CLK_CTRL_REG(t0)
167 and t1, t1, t2
168 sw t1, QCA953X_PLL_CLK_CTRL_REG(t0)
171 li t1, PLL_DDR_DIT_FRAC_VAL
172 sw t1, QCA953X_PLL_DDR_DIT_FRAC_REG(t0)
175 li t1, PLL_CPU_DIT_FRAC_VAL
176 sw t1, QCA953X_PLL_CPU_DIT_FRAC_REG(t0)
180 lui t1, 0x03fc
181 sw t1, 0xb4(t0)