40 	void __iomem *ddr_regs;  in ar934x_ddr_init()  local
45 	ddr_regs = map_physmem(AR71XX_DDR_CTRL_BASE, AR71XX_DDR_CTRL_SIZE,  in ar934x_ddr_init()
67 			writel(0xe59, ddr_regs + AR934X_DDR_REG_DDR2_CONFIG);  in ar934x_ddr_init()
70 			writel(0x10, ddr_regs + AR71XX_DDR_REG_CONTROL);  in ar934x_ddr_init()
73 			writel(0x20, ddr_regs + AR71XX_DDR_REG_CONTROL);  in ar934x_ddr_init()
76 			writel(ctl, ddr_regs + AR934X_DDR_REG_CTL_CONF);  in ar934x_ddr_init()
83 		writel(0x13b, ddr_regs + AR934X_DDR_REG_CTL_CONF);  in ar934x_ddr_init()
87 		writel(0x13b, ddr_regs + 0x118);  in ar934x_ddr_init()
93 	writel(memcfg->config1, ddr_regs + AR71XX_DDR_REG_CONFIG);  in ar934x_ddr_init()
96 	writel(memcfg->config2, ddr_regs + AR71XX_DDR_REG_CONFIG2);  in ar934x_ddr_init()
99 	writel(0x8, ddr_regs + AR71XX_DDR_REG_CONTROL);  in ar934x_ddr_init()
102 	writel(memcfg->mode | 0x100, ddr_regs + AR71XX_DDR_REG_MODE);  in ar934x_ddr_init()
105 	writel(0x1, ddr_regs + AR71XX_DDR_REG_CONTROL);  in ar934x_ddr_init()
109 		writel(memcfg->mode | 0x100, ddr_regs + AR71XX_DDR_REG_EMR);  in ar934x_ddr_init()
112 		writel(0x2, ddr_regs + AR71XX_DDR_REG_CONTROL);  in ar934x_ddr_init()
117 		writel(0x402, ddr_regs + AR71XX_DDR_REG_EMR);  in ar934x_ddr_init()
121 	writel(0x2, ddr_regs + AR71XX_DDR_REG_CONTROL);  in ar934x_ddr_init()
124 	writel(0x8, ddr_regs + AR71XX_DDR_REG_CONTROL);  in ar934x_ddr_init()
127 	writel(memcfg->mode, ddr_regs + AR71XX_DDR_REG_MODE);  in ar934x_ddr_init()
130 	writel(0x1, ddr_regs + AR71XX_DDR_REG_CONTROL);  in ar934x_ddr_init()
133 	writel(0x412c /* FIXME */, ddr_regs + AR71XX_DDR_REG_REFRESH);  in ar934x_ddr_init()
136 	writel(memcfg->tap, ddr_regs + AR71XX_DDR_REG_TAP_CTRL0);  in ar934x_ddr_init()
137 	writel(memcfg->tap, ddr_regs + AR71XX_DDR_REG_TAP_CTRL1);  in ar934x_ddr_init()
142 			       ddr_regs + AR934X_DDR_REG_TAP_CTRL2);  in ar934x_ddr_init()
144 			       ddr_regs + AR934X_DDR_REG_TAP_CTRL3);  in ar934x_ddr_init()
148 	writel(cycle, ddr_regs + AR71XX_DDR_REG_RD_CYCLE);  in ar934x_ddr_init()
151 	writel(0x74444444, ddr_regs + AR934X_DDR_REG_BURST);  in ar934x_ddr_init()
154 	writel(0x222, ddr_regs + AR934X_DDR_REG_BURST2);  in ar934x_ddr_init()
157 	writel(0xfffff, ddr_regs + AR934X_DDR_REG_TIMEOUT_MAX);  in ar934x_ddr_init()