34 	/* Index 0 is for XTAL=25MHz , Index 1 is for XTAL=40MHz */
50 	{ 400, 400, 200, { 0, 1, 1, { 32, 20 } }, { 0, 1, 1, { 32, 20 } } },
51 	{ 500, 400, 200, { 1, 1, 0, { 20, 12 } }, { 0, 1, 1, { 32, 20 } } },
52 	{ 533, 400, 200, { 1, 1, 0, { 21, 13 } }, { 0, 1, 1, { 32, 20 } } },
53 	{ 533, 500, 250, { 1, 1, 0, { 21, 13 } }, { 0, 1, 0, { 20, 12 } } },
54 	{ 560, 480, 240, { 1, 1, 0, { 22, 14 } }, { 1, 1, 0, { 19, 12 } } },
55 	{ 566, 400, 200, { 1, 1, 0, { 22, 14 } }, { 1, 1, 0, { 16, 10 } } },
56 	{ 566, 450, 225, { 1, 1, 0, { 22, 14 } }, { 0, 1, 1, { 36, 22 } } },
57 	{ 566, 475, 237, { 1, 1, 0, { 22, 14 } }, { 1, 1, 0, { 19, 11 } } },
58 	{ 566, 500, 250, { 1, 1, 0, { 22, 14 } }, { 1, 1, 0, { 20, 12 } } },
59 	{ 566, 525, 262, { 1, 1, 0, { 22, 14 } }, { 1, 1, 0, { 21, 13 } } },
60 	{ 566, 550, 275, { 1, 1, 0, { 22, 14 } }, { 1, 1, 0, { 22, 13 } } },
61 	{ 600, 266, 133, { 0, 1, 0, { 24, 15 } }, { 1, 1, 1, { 21, 16 } } },
62 	{ 600, 266, 200, { 0, 1, 0, { 24, 15 } }, { 1, 1, 1, { 21, 16 } } },
63 	{ 600, 300, 150, { 0, 1, 0, { 24, 15 } }, { 0, 1, 1, { 24, 15 } } },
64 	{ 600, 332, 166, { 0, 1, 0, { 24, 15 } }, { 1, 1, 1, { 26, 16 } } },
65 	{ 600, 332, 200, { 0, 1, 0, { 24, 15 } }, { 1, 1, 1, { 26, 16 } } },
66 	{ 600, 400, 200, { 0, 1, 0, { 24, 15 } }, { 0, 1, 1, { 32, 20 } } },
67 	{ 600, 450, 200, { 0, 1, 0, { 24, 15 } }, { 0, 1, 0, { 18, 20 } } },
68 	{ 600, 500, 250, { 0, 1, 0, { 24, 15 } }, { 1, 1, 0, { 20, 12 } } },
69 	{ 600, 525, 262, { 0, 1, 0, { 24, 15 } }, { 0, 1, 0, { 21, 20 } } },
70 	{ 600, 550, 275, { 0, 1, 0, { 24, 15 } }, { 0, 1, 0, { 22, 20 } } },
71 	{ 600, 575, 287, { 0, 1, 0, { 24, 15 } }, { 0, 1, 0, { 23, 14 } } },
72 	{ 600, 600, 300, { 0, 1, 0, { 24, 15 } }, { 0, 1, 0, { 24, 20 } } },
73 	{ 600, 650, 325, { 0, 1, 0, { 24, 15 } }, { 0, 1, 0, { 26, 20 } } },
74 	{ 650, 600, 300, { 0, 1, 0, { 26, 15 } }, { 0, 1, 0, { 24, 20 } } },
75 	{ 700, 400, 200, { 3, 1, 0, { 28, 17 } }, { 0, 1, 1, { 32, 20 } } },
82 		writel(0x10810f00, pll_reg_base + 0x4);  in ar934x_srif_pll_cfg()
83 		writel(srif_val, pll_reg_base + 0x0);  in ar934x_srif_pll_cfg()
84 		writel(0xd0810f00, pll_reg_base + 0x4);  in ar934x_srif_pll_cfg()
85 		writel(0x03000000, pll_reg_base + 0x8);  in ar934x_srif_pll_cfg()
86 		writel(0xd0800f00, pll_reg_base + 0x4);  in ar934x_srif_pll_cfg()
88 		clrbits_be32(pll_reg_base + 0x8, BIT(30));  in ar934x_srif_pll_cfg()
90 		setbits_be32(pll_reg_base + 0x8, BIT(30));  in ar934x_srif_pll_cfg()
93 		wait_for_bit_le32(pll_reg_base + 0xc, BIT(3), 1, 10, 0);  in ar934x_srif_pll_cfg()
95 		clrbits_be32(pll_reg_base + 0x8, BIT(30));  in ar934x_srif_pll_cfg()
99 		reg = readl(pll_reg_base + 0x8);  in ar934x_srif_pll_cfg()
100 		reg = (reg & 0x7ffff8) >> 3;  in ar934x_srif_pll_cfg()
101 	} while (reg >= 0x40000);  in ar934x_srif_pll_cfg()
111 	int i, pll_nint, pll_refdiv, xtal_40 = 0;  in ar934x_pll_init()
115 	writel(0x13210f00, srif_regs + AR934X_SRIF_CPU_DPLL2_REG);  in ar934x_pll_init()
116 	writel(0x03000000, srif_regs + AR934X_SRIF_CPU_DPLL3_REG);  in ar934x_pll_init()
117 	writel(0x13210f00, srif_regs + AR934X_SRIF_DDR_DPLL2_REG);  in ar934x_pll_init()
118 	writel(0x03000000, srif_regs + AR934X_SRIF_DDR_DPLL3_REG);  in ar934x_pll_init()
119 	writel(0x03000000, srif_regs + 0x188); /* Undocumented reg :-) */  in ar934x_pll_init()
125 		cpu_srif = 0x41c00000;  in ar934x_pll_init()
126 		ddr_srif = 0x41680000;  in ar934x_pll_init()
128 		xtal_40 = 0;  in ar934x_pll_init()
129 		cpu_srif = 0x29c00000;  in ar934x_pll_init()
130 		ddr_srif = 0x29680000;  in ar934x_pll_init()
134 	for (i = 0; i < ARRAY_SIZE(ar934x_clock_config); i++) {  in ar934x_pll_init()
185 	       (0 << AR934X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) |  in ar934x_pll_init()
186 	       (0 << AR934X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) |  in ar934x_pll_init()
207 	       (0xf << AR934X_PLL_DDR_DIT_UPD_CNT_SHIFT),  in ar934x_pll_init()
327 	return 0;  in do_ar934x_showclk()