Lines Matching refs:t1
83 lw t1, AR933X_RESET_REG_RESET_MODULE(t0)
84 ori t1, t1, 0x0800
85 sw t1, AR933X_RESET_REG_RESET_MODULE(t0)
87 lw t1, AR933X_RESET_REG_RESET_MODULE(t0)
89 and t1, t1, t2
90 sw t1, AR933X_RESET_REG_RESET_MODULE(t0)
102 andi t1, t5, 0x10
103 bnez t1, 2b
106 li t1, 0x02110E
107 sw t1, AR933X_RESET_REG_BOOTSTRAP(t0)
112 li t1, 0x03
113 sw t1, AR933X_RTC_REG_FORCE_WAKE(t0)
118 li t1, 0x00
119 sw t1, AR933X_RTC_REG_RESET(t0)
123 li t1, 0x01
124 sw t1, AR933X_RTC_REG_RESET(t0)
130 lw t1, AR933X_RTC_REG_STATUS(t0)
131 andi t1, t1, 0x02
132 beqz t1, 1b
137 andi t1, t5, 0x01 # t5 BOOT_STRAP
138 bnez t1, 1f
140 li t1, 0x19e82f01
144 li t1, 0x18e82f01
146 sw t1, AR933X_SRIF_DDR_DPLL2_REG(t0)
149 lw t1, AR933X_SRIF_DDR_DPLL3_REG(t0)
151 and t1, t1, t2
153 or t1, t1, t2
154 sw t1, AR933X_SRIF_DDR_DPLL3_REG(t0)
159 li t1, AHB_DIV_TO_4(PLL_BYPASS(PLL_CLK_CONTROL_VAL))
160 sw t1, AR933X_PLL_CLK_CTRL_REG(t0)
164 andi t1, t5, 0x01 # t5 BOOT_STRAP
165 bnez t1, 1f
167 li t1, 0x0352
171 li t1, 0x0550
173 sw t1, AR71XX_PLL_REG_SEC_CONFIG(t0)
178 andi t1, t5, 0x01 # t5 BOOT_STRAP
179 bnez t1, 1f
181 li t1, SET_PLL_PD(PLL_CPU_CONFIG_VAL_25M)
185 li t1, SET_PLL_PD(PLL_CPU_CONFIG_VAL_40M)
187 sw t1, AR933X_PLL_CPU_CONFIG_REG(t0)
190 lw t1, AR933X_PLL_CPU_CONFIG_REG(t0)
192 and t1, t1, t2
193 bnez t1, 1b
197 li t1, 0x1003E8
198 sw t1, AR933X_PLL_DITHER_FRAC_REG(t0)
202 andi t1, t5, 0x01 # t5 BOOT_STRAP
203 bnez t1, 1f
205 li t1, PLL_CPU_CONFIG_VAL_25M
209 li t1, PLL_CPU_CONFIG_VAL_40M
211 sw t1, AR933X_PLL_CPU_CONFIG_REG(t0)
216 lw t1, AR933X_PLL_CPU_CONFIG_REG(t0)
218 and t1, t1, t2
219 bnez t1, 1b
235 lw t1, AR933X_SRIF_DDR_DPLL3_REG(t0)
237 and t1, t1, t2
238 sw t1, AR933X_SRIF_DDR_DPLL3_REG(t0)
249 or t1, t1, t2
250 sw t1, AR933X_SRIF_DDR_DPLL3_REG(t0)
255 lw t1, AR933X_SRIF_DDR_DPLL4_REG(t0)
256 andi t1, t1, 0x8
257 beqz t1, 1b
260 lw t1, AR933X_SRIF_DDR_DPLL3_REG(t0)
262 and t1, t1, t2
263 srl t1, t1, 3
265 bgt t1, t2, 2b
273 li t1, PLL_CLK_CONTROL_VAL
274 sw t1, AR933X_PLL_CLK_CTRL_REG(t0)