mips/lib/cache_init.S

126 	mfc0	t0, CP0_CONFIG, 1
127 	bgez	t0, l2_probe_done
137 	mfc0	t0, CP0_CONFIG, 2
138 	bgez	t0, l2_probe_cop0
139 	mfc0	t0, CP0_CONFIG, 3
140 	bgez	t0, l2_probe_cop0
141 	mfc0	t0, CP0_CONFIG, 4
142 	bgez	t0, l2_probe_cop0
145 	mfc0	t0, CP0_CONFIG, 5
146 	and	R_L2_L2C, t0, MIPS_CONF5_L2C
152 	PTR_LI	t0, CKSEG1ADDR(CONFIG_MIPS_CM_BASE)
153 	lw	t1, GCR_L2_CONFIG(t0)
173 	sw	t1, GCR_L2_CONFIG(t0)
178 	sw	zero, GCR_L2_TAG_ADDR(t0)
179 	sw	zero, GCR_L2_TAG_ADDR_UPPER(t0)
180 	sw	zero, GCR_L2_TAG_STATE(t0)
181 	sw	zero, GCR_L2_TAG_STATE_UPPER(t0)
182 	sw	zero, GCR_L2_DATA(t0)
183 	sw	zero, GCR_L2_DATA_UPPER(t0)
196 	mfc0	t0, CP0_CONFIG, 2
198 	srl	R_L2_LINE, t0, MIPS_CONF2_SL_SHF
204 	srl	t1, t0, MIPS_CONF2_SA_SHF
209 	srl	t1, t0, MIPS_CONF2_SS_SHF
216 	or	t0, t0, MIPS_CONF2_L2B
217 	mtc0	t0, CP0_CONFIG, 2
219 	mfc0	t0, CP0_CONFIG, 2
220 	and	R_L2_BYPASSED, t0, MIPS_CONF2_L2B
275 	PTR_LI		t0, INDEX_BASE
276 	PTR_ADDU	t1, t0, R_L2_SIZE
277 1:	cache		INDEX_STORE_TAG_SD, 0(t0)
278 	PTR_ADDU	t0, t0, R_L2_LINE
279 	bne		t0, t1, 1b
311 	PTR_LI		t0, INDEX_BASE
312 	PTR_ADDU	t1, t0, R_IC_SIZE
314 	cache_loop	t0, t1, R_IC_LINE, INDEX_STORE_TAG_I
317 	PTR_LI		t0, INDEX_BASE
318 	cache_loop	t0, t1, R_IC_LINE, FILL
320 	PTR_LI		t0, INDEX_BASE
321 	cache_loop	t0, t1, R_IC_LINE, INDEX_STORE_TAG_I
326 	mfc0		t0, CP0_CONFIG
329 	ins		t0, t1, 0, 3
331 	ori		t0, t0, CONF_CM_CMASK
332 	xori		t0, t0, CONF_CM_CMASK
333 	or		t0, t0, t1
335 	mtc0		t0, CP0_CONFIG
341 	PTR_LI		t0, INDEX_BASE
342 	PTR_ADDU	t1, t0, R_DC_SIZE
344 	cache_loop	t0, t1, R_DC_LINE, INDEX_STORE_TAG_D
347 	PTR_LI		t0, INDEX_BASE
348 2:	LONG_L		zero, 0(t0)
349 	PTR_ADDU	t0, R_DC_LINE
350 	bne		t0, t1, 2b
352 	PTR_LI		t0, INDEX_BASE
353 	cache_loop	t0, t1, R_DC_LINE, INDEX_STORE_TAG_D
368 	li		t0, CKSEG1ADDR(CONFIG_MIPS_CM_BASE)
369 	lw		t1, GCR_L2_CONFIG(t0)
371 	sw		t1, GCR_L2_CONFIG(t0)
376 1:	mfc0		t0, CP0_CONFIG, 2
377 	xor		t0, t0, MIPS_CONF2_L2B
378 	mtc0		t0, CP0_CONFIG, 2
384 	mfc0		t0, CP0_CONFIG, 1
385 	bgez		t0, 2f
386 	mfc0		t0, CP0_CONFIG, 2
387 	bgez		t0, 2f
390 	mfc0		t0, CP0_CONFIG, 3
391 	and		t0, t0, MIPS_CONF3_CMGCR
392 	beqz		t0, 2f
395 	mfc0		t0, CP0_CONFIG
398 	ins		t0, t1, 0, 3
400 	ori		t0, t0, CONF_CM_CMASK
401 	xori		t0, t0, CONF_CM_CMASK
402 	or		t0, t0, t1
404 	mtc0		t0, CP0_CONFIG
410 	PTR_LI		t0, CKSEG1ADDR(CONFIG_MIPS_CM_BASE)
411 	lw		t1, GCR_REV(t0)
416 1:	sw		t3, GCR_Cx_COHERENCE(t0)
435 	mfc0	t0, CP0_CONFIG
437 	andi	t0, t0, CONF_CM_CMASK
439 	beq	t0, t1, 2f
451 	mfc0	t0, CP0_CONFIG
453 	and	t0, t0, t1
454 	ori	t0, t0, CONF_CM_UNCACHED
455 	mtc0	t0, CP0_CONFIG
466 	mfc0	t0, CP0_CONFIG
467 	ori	t0, CONF_CM_CMASK
468 	xori	t0, CONF_CM_CMASK
469 	ori	t0, CONFIG_SYS_MIPS_CACHE_MODE
470 	mtc0	t0, CP0_CONFIG