Lines Matching refs:t1
153 lw t1, GCR_L2_CONFIG(t0)
154 bgez t1, l2_probe_done
156 ext R_L2_LINE, t1, \
162 ext t2, t1, GCR_L2_CONFIG_ASSOC_SHIFT, GCR_L2_CONFIG_ASSOC_BITS
166 ext t2, t1, GCR_L2_CONFIG_SETSZ_SHIFT, GCR_L2_CONFIG_SETSZ_BITS
172 or t1, t1, GCR_L2_CONFIG_BYPASS
173 sw t1, GCR_L2_CONFIG(t0)
201 li t1, 2
202 sllv R_L2_LINE, t1, R_L2_LINE
204 srl t1, t0, MIPS_CONF2_SA_SHF
205 andi t1, t1, MIPS_CONF2_SA >> MIPS_CONF2_SA_SHF
206 addiu t1, t1, 1
207 mul R_L2_SIZE, R_L2_LINE, t1
209 srl t1, t0, MIPS_CONF2_SS_SHF
210 andi t1, t1, MIPS_CONF2_SS >> MIPS_CONF2_SS_SHF
211 sllv R_L2_SIZE, R_L2_SIZE, t1
212 li t1, 64
213 mul R_L2_SIZE, R_L2_SIZE, t1
253 sltu t1, R_IC_SIZE, R_DC_SIZE
254 movn v0, R_DC_SIZE, t1
276 PTR_ADDU t1, t0, R_L2_SIZE
279 bne t0, t1, 1b
312 PTR_ADDU t1, t0, R_IC_SIZE
314 cache_loop t0, t1, R_IC_LINE, INDEX_STORE_TAG_I
318 cache_loop t0, t1, R_IC_LINE, FILL
321 cache_loop t0, t1, R_IC_LINE, INDEX_STORE_TAG_I
327 li t1, CONFIG_SYS_MIPS_CACHE_MODE
329 ins t0, t1, 0, 3
333 or t0, t0, t1
342 PTR_ADDU t1, t0, R_DC_SIZE
344 cache_loop t0, t1, R_DC_LINE, INDEX_STORE_TAG_D
350 bne t0, t1, 2b
353 cache_loop t0, t1, R_DC_LINE, INDEX_STORE_TAG_D
369 lw t1, GCR_L2_CONFIG(t0)
370 xor t1, t1, GCR_L2_CONFIG_BYPASS
371 sw t1, GCR_L2_CONFIG(t0)
396 li t1, CONF_CM_CACHABLE_COW
398 ins t0, t1, 0, 3
402 or t0, t0, t1
411 lw t1, GCR_REV(t0)
414 bge t1, t2, 1f
436 li t1, CONF_CM_UNCACHED
439 beq t0, t1, 2f
452 li t1, -8
453 and t0, t0, t1