Lines Matching +full:0 +full:x40410000
35 * Coprocessor 0 register names
37 #define CP0_INDEX $0
47 #define CP0_HWRENA $7, 0
84 #define CP0_IBASE $0
93 * Coprocessor 0 Set 1 register names
100 * Coprocessor 0 Set 2 register names
105 * Coprocessor 0 Set 3 register names
116 #define ENTRYLO_G (_ULCAST_(1) << 0)
140 #define PM_1K 0x00000000
141 #define PM_4K 0x00001800
142 #define PM_16K 0x00007800
143 #define PM_64K 0x0001f800
144 #define PM_256K 0x0007f800
148 #define PM_4K 0x00000000
149 #define PM_8K 0x00002000
150 #define PM_16K 0x00006000
151 #define PM_32K 0x0000e000
152 #define PM_64K 0x0001e000
153 #define PM_128K 0x0003e000
154 #define PM_256K 0x0007e000
155 #define PM_512K 0x000fe000
156 #define PM_1M 0x001fe000
157 #define PM_2M 0x003fe000
158 #define PM_4M 0x007fe000
159 #define PM_8M 0x00ffe000
160 #define PM_16M 0x01ffe000
161 #define PM_32M 0x03ffe000
162 #define PM_64M 0x07ffe000
163 #define PM_256M 0x1fffe000
164 #define PM_1G 0x7fffe000
220 #define ST0_IE 0x00000001
221 #define ST0_EXL 0x00000002
222 #define ST0_ERL 0x00000004
223 #define ST0_KSU 0x00000018
224 # define KSU_USER 0x00000010
225 # define KSU_SUPERVISOR 0x00000008
226 # define KSU_KERNEL 0x00000000
227 #define ST0_UX 0x00000020
228 #define ST0_SX 0x00000040
229 #define ST0_KX 0x00000080
230 #define ST0_DE 0x00010000
231 #define ST0_CE 0x00020000
238 #define ST0_CO 0x08000000
243 #define ST0_IEC 0x00000001
244 #define ST0_KUC 0x00000002
245 #define ST0_IEP 0x00000004
246 #define ST0_KUP 0x00000008
247 #define ST0_IEO 0x00000010
248 #define ST0_KUO 0x00000020
250 #define ST0_ISC 0x00010000
251 #define ST0_SWC 0x00020000
252 #define ST0_CM 0x00080000
264 #define ST0_MX 0x01000000
269 #define ST0_IM 0x0000ff00
286 #define STATUSB_IP8 0
287 #define STATUSF_IP8 (_ULCAST_(1) << 0)
303 #define ST0_CH 0x00040000
304 #define ST0_NMI 0x00080000
305 #define ST0_SR 0x00100000
306 #define ST0_TS 0x00200000
307 #define ST0_BEV 0x00400000
308 #define ST0_RE 0x02000000
309 #define ST0_FR 0x04000000
310 #define ST0_CU 0xf0000000
311 #define ST0_CU0 0x10000000
312 #define ST0_CU1 0x20000000
313 #define ST0_CU2 0x40000000
314 #define ST0_CU3 0x80000000
315 #define ST0_XX 0x80000000 /* MIPS IV naming */
318 * Bitfields and bit numbers in the coprocessor 0 IntCtl register. (MIPSR2)
328 * Bitfields and bit numbers in the coprocessor 0 cause register.
366 * Bits in the coprocessor 0 EBase register.
368 #define EBASE_CPUNUM 0x3ff
371 * Bits in the coprocessor 0 config register.
374 #define CONF_CM_CACHABLE_NO_WA 0
460 #define MIPS_CONF_IMPL (_ULCAST_(0x1ff) << 16)
464 * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
466 #define MIPS_CONF1_FP (_ULCAST_(1) << 0)
495 #define MIPS_CONF2_SA_SHF 0
496 #define MIPS_CONF2_SA (_ULCAST_(15) << 0)
508 #define MIPS_CONF3_TL (_ULCAST_(1) << 0)
536 #define MIPS_CONF4_MMUSIZEEXT_SHIFT (0)
537 #define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0)
538 #define MIPS_CONF4_FTLBSETS_SHIFT (0)
558 #define MIPS_CONF5_NF (_ULCAST_(1) << 0)
591 #define MIPS_MAAR_V (_ULCAST_(1) << 0)
606 #define MIPS_SEGCFG_C_SHIFT 0
615 #define MIPS_SEGCFG_UK _ULCAST_(0)
618 #define MIPS_PWFIELD_GDI_MASK 0x3f000000
620 #define MIPS_PWFIELD_UDI_MASK 0x00fc0000
622 #define MIPS_PWFIELD_MDI_MASK 0x0003f000
624 #define MIPS_PWFIELD_PTI_MASK 0x00000fc0
625 #define MIPS_PWFIELD_PTEI_SHIFT 0
626 #define MIPS_PWFIELD_PTEI_MASK 0x0000003f
629 #define MIPS_PWSIZE_GDW_MASK 0x3f000000
631 #define MIPS_PWSIZE_UDW_MASK 0x00fc0000
633 #define MIPS_PWSIZE_MDW_MASK 0x0003f000
635 #define MIPS_PWSIZE_PTW_MASK 0x00000fc0
636 #define MIPS_PWSIZE_PTEW_SHIFT 0
637 #define MIPS_PWSIZE_PTEW_MASK 0x0000003f
640 #define MIPS_PWCTL_PWEN_MASK 0x80000000
642 #define MIPS_PWCTL_DPH_MASK 0x00000080
644 #define MIPS_PWCTL_HUGEPG_MASK 0x00000060
645 #define MIPS_PWCTL_PSN_SHIFT 0
646 #define MIPS_PWCTL_PSN_MASK 0x0000003f
649 #define MIPS_CDMMBASE_SIZE_SHIFT 0
660 #define TX39_CONF_ICS_MASK 0x00380000
661 #define TX39_CONF_ICS_1KB 0x00000000
662 #define TX39_CONF_ICS_2KB 0x00080000
663 #define TX39_CONF_ICS_4KB 0x00100000
664 #define TX39_CONF_ICS_8KB 0x00180000
665 #define TX39_CONF_ICS_16KB 0x00200000
668 #define TX39_CONF_DCS_MASK 0x00070000
669 #define TX39_CONF_DCS_1KB 0x00000000
670 #define TX39_CONF_DCS_2KB 0x00010000
671 #define TX39_CONF_DCS_4KB 0x00020000
672 #define TX39_CONF_DCS_8KB 0x00030000
673 #define TX39_CONF_DCS_16KB 0x00040000
675 #define TX39_CONF_CWFON 0x00004000
676 #define TX39_CONF_WBON 0x00002000
678 #define TX39_CONF_RF_MASK 0x00000c00
679 #define TX39_CONF_DOZE 0x00000200
680 #define TX39_CONF_HALT 0x00000100
681 #define TX39_CONF_LOCK 0x00000080
682 #define TX39_CONF_ICE 0x00000020
683 #define TX39_CONF_DCE 0x00000010
685 #define TX39_CONF_IRSIZE_MASK 0x0000000c
686 #define TX39_CONF_DRSIZE_SHIFT 0
687 #define TX39_CONF_DRSIZE_MASK 0x00000003
702 #define CP1_REVISION $0
728 #define MIPS_FCCR_CONDX_S 0
730 #define MIPS_FCCR_COND0_S 0
759 #define FPU_CSR_FS_S 24 /* flush denormalised results to 0 */
780 * Bits 22:20 of the FPU Status Register will be read as 0,
793 #define FPU_CSR_ALL_X 0x0003f000
794 #define FPU_CSR_UNI_X 0x00020000
795 #define FPU_CSR_INV_X 0x00010000
796 #define FPU_CSR_DIV_X 0x00008000
797 #define FPU_CSR_OVF_X 0x00004000
798 #define FPU_CSR_UDF_X 0x00002000
799 #define FPU_CSR_INE_X 0x00001000
801 #define FPU_CSR_ALL_E 0x00000f80
802 #define FPU_CSR_INV_E 0x00000800
803 #define FPU_CSR_DIV_E 0x00000400
804 #define FPU_CSR_OVF_E 0x00000200
805 #define FPU_CSR_UDF_E 0x00000100
806 #define FPU_CSR_INE_E 0x00000080
808 #define FPU_CSR_ALL_S 0x0000007c
809 #define FPU_CSR_INV_S 0x00000040
810 #define FPU_CSR_DIV_S 0x00000020
811 #define FPU_CSR_OVF_S 0x00000010
812 #define FPU_CSR_UDF_S 0x00000008
813 #define FPU_CSR_INE_S 0x00000004
815 /* Bits 0 and 1 of FPU Status Register specify the rounding mode */
816 #define FPU_CSR_RM 0x00000003
817 #define FPU_CSR_RN 0x0 /* nearest */
818 #define FPU_CSR_RZ 0x1 /* towards zero */
819 #define FPU_CSR_RU 0x2 /* towards +Infinity */
820 #define FPU_CSR_RD 0x3 /* towards -Infinity */
830 #define get_isa16_mode(x) ((x) & 0x1)
831 #define msk_isa16_mode(x) ((x) & ~0x1)
832 #define set_isa16_mode(x) do { (x) |= 0x1; } while (0)
834 #define get_isa16_mode(x) 0
836 #define set_isa16_mode(x) do { } while (0)
841 * returns a 1 if the instruction is 16-bit and a 0 if 32-bit.
845 u16 opcode = (insn >> 10) & 0x7; in mm_insn_16bit()
847 return (opcode >= 1 && opcode <= 3) ? 1 : 0; in mm_insn_16bit()
858 ".word 0x42000004\n\t" /* tlbinvf */ in tlbinvf()
867 * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware
868 * disassembler these will look like an access to sel 0 or 1.
874 "mfpc\t%0, %1" \
884 "mtpc\t%0, %1" \
887 } while (0)
893 "mfps\t%0, %1" \
903 "mtps\t%0, %1" \
906 } while (0)
915 if (sel == 0) \
917 "mfc0\t%0, " #source "\n\t" \
922 "mfc0\t%0, " #source ", " #sel "\n\t" \
932 else if (sel == 0) \
935 "dmfc0\t%0, " #source "\n\t" \
941 "dmfc0\t%0, " #source ", " #sel "\n\t" \
949 if (sel == 0) \
959 } while (0)
965 else if (sel == 0) \
977 } while (0)
990 } while (0)
998 "cfc0\t%0, " #source "\n\t" \
1008 } while (0)
1020 if (sel == 0) \
1048 if (sel == 0) \
1069 } while (0)
1081 " .word (0x40410000 | ((%1 & 0x1f) << 11)) \n" \
1082 " move %0, $1 \n" \
1095 " move $1, %0 \n" \
1098 " .word (0x40c10000 | ((%1 & 0x1f) << 11)) \n" \
1104 #define read_c0_index() __read_32bit_c0_register($0, 0)
1105 #define write_c0_index(val) __write_32bit_c0_register($0, 0, val)
1107 #define read_c0_random() __read_32bit_c0_register($1, 0)
1108 #define write_c0_random(val) __write_32bit_c0_register($1, 0, val)
1110 #define read_c0_entrylo0() __read_ulong_c0_register($2, 0)
1111 #define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val)
1116 #define read_c0_entrylo1() __read_ulong_c0_register($3, 0)
1117 #define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val)
1122 #define read_c0_conf() __read_32bit_c0_register($3, 0)
1123 #define write_c0_conf(val) __write_32bit_c0_register($3, 0, val)
1125 #define read_c0_context() __read_ulong_c0_register($4, 0)
1126 #define write_c0_context(val) __write_ulong_c0_register($4, 0, val)
1131 #define read_c0_pagemask() __read_32bit_c0_register($5, 0)
1132 #define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val)
1137 #define read_c0_wired() __read_32bit_c0_register($6, 0)
1138 #define write_c0_wired(val) __write_32bit_c0_register($6, 0, val)
1140 #define read_c0_info() __read_32bit_c0_register($7, 0)
1142 #define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */
1143 #define write_c0_cache(val) __write_32bit_c0_register($7, 0, val)
1145 #define read_c0_badvaddr() __read_ulong_c0_register($8, 0)
1146 #define write_c0_badvaddr(val) __write_ulong_c0_register($8, 0, val)
1148 #define read_c0_count() __read_32bit_c0_register($9, 0)
1149 #define write_c0_count(val) __write_32bit_c0_register($9, 0, val)
1157 #define read_c0_entryhi() __read_ulong_c0_register($10, 0)
1158 #define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val)
1160 #define read_c0_compare() __read_32bit_c0_register($11, 0)
1161 #define write_c0_compare(val) __write_32bit_c0_register($11, 0, val)
1169 #define read_c0_status() __read_32bit_c0_register($12, 0)
1171 #define write_c0_status(val) __write_32bit_c0_register($12, 0, val)
1173 #define read_c0_cause() __read_32bit_c0_register($13, 0)
1174 #define write_c0_cause(val) __write_32bit_c0_register($13, 0, val)
1176 #define read_c0_epc() __read_ulong_c0_register($14, 0)
1177 #define write_c0_epc(val) __write_ulong_c0_register($14, 0, val)
1179 #define read_c0_prid() __read_32bit_c0_register($15, 0)
1183 #define read_c0_config() __read_32bit_c0_register($16, 0)
1191 #define write_c0_config(val) __write_32bit_c0_register($16, 0, val)
1200 #define read_c0_lladdr() __read_ulong_c0_register($17, 0)
1201 #define write_c0_lladdr(val) __write_ulong_c0_register($17, 0, val)
1210 #define read_c0_watchlo0() __read_ulong_c0_register($18, 0)
1218 #define write_c0_watchlo0(val) __write_ulong_c0_register($18, 0, val)
1230 #define read_c0_watchhi0() __read_32bit_c0_register($19, 0)
1239 #define write_c0_watchhi0(val) __write_32bit_c0_register($19, 0, val)
1248 #define read_c0_xcontext() __read_ulong_c0_register($20, 0)
1249 #define write_c0_xcontext(val) __write_ulong_c0_register($20, 0, val)
1254 #define read_c0_framemask() __read_32bit_c0_register($21, 0)
1255 #define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
1257 #define read_c0_diag() __read_32bit_c0_register($22, 0)
1258 #define write_c0_diag(val) __write_32bit_c0_register($22, 0, val)
1261 #define read_c0_r10k_diag() __read_64bit_c0_register($22, 0)
1262 #define write_c0_r10k_diag(val) __write_64bit_c0_register($22, 0, val)
1279 #define read_c0_debug() __read_32bit_c0_register($23, 0)
1280 #define write_c0_debug(val) __write_32bit_c0_register($23, 0, val)
1282 #define read_c0_depc() __read_ulong_c0_register($24, 0)
1283 #define write_c0_depc(val) __write_ulong_c0_register($24, 0, val)
1288 #define read_c0_perfctrl0() __read_32bit_c0_register($25, 0)
1289 #define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val)
1313 #define read_c0_ecc() __read_32bit_c0_register($26, 0)
1314 #define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val)
1319 #define read_c0_cacheerr() __read_32bit_c0_register($27, 0)
1324 #define read_c0_taglo() __read_32bit_c0_register($28, 0)
1325 #define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val)
1336 #define read_c0_taghi() __read_32bit_c0_register($29, 0)
1337 #define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val)
1339 #define read_c0_errorepc() __read_ulong_c0_register($30, 0)
1340 #define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val)
1343 #define read_c0_hwrena() __read_32bit_c0_register($7, 0)
1344 #define write_c0_hwrena(val) __write_32bit_c0_register($7, 0, val)
1397 #define read_octeon_c0_icacheerr() __read_64bit_c0_register($27, 0)
1398 #define write_octeon_c0_icacheerr(val) __write_64bit_c0_register($27, 0, val)
1404 #define read_c0_brcm_config_0() __read_32bit_c0_register($22, 0)
1405 #define write_c0_brcm_config_0(val) __write_32bit_c0_register($22, 0, val)
1430 #define read_c0_brcm_config() __read_32bit_c0_register($22, 0)
1431 #define write_c0_brcm_config(val) __write_32bit_c0_register($22, 0, val)
1462 " cfc1 %0,"STR(source)" \n" \
1474 " ctc1 %0,"STR(dest)" \n" \
1499 " rddsp %0, %x1 \n" \
1511 " wrdsp %0, %x1 \n" \
1523 " mflo %0, $ac0 \n" \
1535 " mflo %0, $ac1 \n" \
1547 " mflo %0, $ac2 \n" \
1559 " mflo %0, $ac3 \n" \
1571 " mfhi %0, $ac0 \n" \
1583 " mfhi %0, $ac1 \n" \
1595 " mfhi %0, $ac2 \n" \
1607 " mfhi %0, $ac3 \n" \
1619 " mtlo %0, $ac0 \n" \
1630 " mtlo %0, $ac1 \n" \
1641 " mtlo %0, $ac2 \n" \
1652 " mtlo %0, $ac3 \n" \
1663 " mthi %0, $ac0 \n" \
1674 " mthi %0, $ac1 \n" \
1685 " mthi %0, $ac2 \n" \
1696 " mthi %0, $ac3 \n" \
1713 " .hword ((0x0020067c | (%x1 << 14)) >> 16) \n" \
1714 " .hword ((0x0020067c | (%x1 << 14)) & 0xffff) \n" \
1715 " move %0, $1 \n" \
1727 " move $1, %0 \n" \
1729 " .hword ((0x0020167c | (%x1 << 14)) >> 16) \n" \
1730 " .hword ((0x0020167c | (%x1 << 14)) & 0xffff) \n" \
1743 " .hword 0x0001 \n" \
1745 " move %0, $1 \n" \
1757 " move $1, %0 \n" \
1758 " .hword 0x0001 \n" \
1765 #define _umips_dsp_mflo(reg) _umips_dsp_mfxxx((reg << 14) | 0x107c)
1766 #define _umips_dsp_mfhi(reg) _umips_dsp_mfxxx((reg << 14) | 0x007c)
1768 #define _umips_dsp_mtlo(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x307c))
1769 #define _umips_dsp_mthi(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x207c))
1771 #define mflo0() _umips_dsp_mflo(0)
1776 #define mfhi0() _umips_dsp_mfhi(0)
1781 #define mtlo0(x) _umips_dsp_mtlo(x, 0)
1786 #define mthi0(x) _umips_dsp_mthi(x, 0)
1800 " .word 0x7c000cb8 | (%x1 << 16) \n" \
1801 " move %0, $1 \n" \
1813 " move $1, %0 \n" \
1815 " .word 0x7c2004f8 | (%x1 << 11) \n" \
1828 " .word (0x00000810 | %1) \n" \
1829 " move %0, $1 \n" \
1841 " move $1, %0 \n" \
1842 " .word (0x00200011 | %1) \n" \
1848 #define _dsp_mflo(reg) _dsp_mfxxx((reg << 21) | 0x0002)
1849 #define _dsp_mfhi(reg) _dsp_mfxxx((reg << 21) | 0x0000)
1851 #define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0002))
1852 #define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0000))
1854 #define mflo0() _dsp_mflo(0)
1859 #define mfhi0() _dsp_mfhi(0)
1864 #define mtlo0(x) _dsp_mtlo(x, 0)
1869 #define mthi0(x) _dsp_mthi(x, 0)
1893 int res = 0; in tlb_read()
1900 " .word 0x41610001 # dvpe $1 \n" in tlb_read()
1901 " move %0, $1 \n" in tlb_read()
1921 " .word 0x41600021 # evpe \n" in tlb_read()
2006 return read_c0_ebase() & 0x3ff; in __BUILD_SET_C0()