Lines Matching +full:sw +full:- +full:exception

2  *  Startup Code for MIPS32 CPU-core
6  * SPDX-License-Identifier:	GPL-2.0+
9 #include <asm-offsets.h>
50 	li	t9, 15		# UHI exception operation
56 	li	t0, -16
79 	PTR_S	sp, GD_MALLOC_BASE(k0)	# gd->malloc_base offset
84 	/* U-Boot entry point */
94 	 * device with correct parameters. This config option is board-specific.
111 	 * Exception vector entry points. When running from ROM, an exception
124 	/* Cache error exception */
128 	/* General exception */
136 	/* EJTAG debug exception */
210 	/* Clear WP, IV and SW interrupts */
275 	move	a0, zero		# a0 <-- boot_flags = 0