Lines Matching refs:r0

24 	mts	rmsr, r0	/* disable cache */
26 	addi	r8, r0, __end
30 	addi	r1, r0, CONFIG_SPL_STACK_ADDR
35 	addi	r1, r0, CONFIG_SYS_INIT_SP_OFFSET - CONFIG_VAL(SYS_MALLOC_F_LEN)
37 	addi	r1, r0, CONFIG_SYS_INIT_SP_OFFSET
51 	addik	r6, r0, 0x2 /* BIG/LITTLE endian offset */
52 	lwi	r7, r0, 0x28
53 	swi	r6, r0, 0x28 /* used first unused MB vector */
54 	lbui	r10, r0, 0x28 /* used first unused MB vector */
55 	swi	r7, r0, 0x28
58 	addi	r2, r0, 0xb0000000	/* hex b000 opcode imm */
59 	addi	r3, r0, 0xb8080000	/* hew b808 opcode brai */
63 	swi	r2, r0, 0x0	/* reset address - imm opcode */
64 	swi	r3, r0, 0x4	/* reset address - brai opcode */
66 	addik	r6, r0, CONFIG_SYS_RESET_ADDRESS
67 	sw	r6, r1, r0
70 	sh	r7, r0, r8
72 	sh	r6, r0, r8
77 	swi	r2, r0, 0x8	/* user vector exception - imm opcode */
78 	swi	r3, r0, 0xC	/* user vector exception - brai opcode */
80 	addik	r6, r0, _exception_handler
81 	sw	r6, r1, r0
104 	sh	r7, r0, r8
106 	sh	r6, r0, r8
110 	swi	r2, r0, 0x10	/* interrupt - imm opcode */
111 	swi	r3, r0, 0x14	/* interrupt - brai opcode */
113 	addik	r6, r0, _interrupt_handler
114 	sw	r6, r1, r0
117 	sh	r7, r0, r8
119 	sh	r6, r0, r8
122 	swi	r2, r0, 0x20	/* hardware exception - imm opcode */
123 	swi	r3, r0, 0x24	/* hardware exception - brai opcode */
125 	addik	r6, r0, _hw_exception_handler
126 	sw	r6, r1, r0
129 	sh	r7, r0, r8
131 	sh	r6, r0, r8
135 	addik	r5, r0, 0
136 	addik	r6, r0, XILINX_DCACHE_BYTE_SIZE
148 	addi	r5, r0, __bss_start
149 	addi	r4, r0, __bss_end
153 	swi     r0, r5, 0 /* write zero to loc */
163 	or	r5, r0, r0	/* flags - empty */
164 	addi    r31, r0, _gd
166 	addi	r6, r0, CONFIG_SYS_INIT_SP_OFFSET
171 	addi	r31, r0, _gd
173 	addi	r6, r0, CONFIG_SPL_STACK_ADDR
193 in16:	lhu	r3, r0, r5
214 	sh	r3, r0, r5
216 	or	r0, r0, r0
235 	add	r23, r0, r7 /* Move reloc addr to r23 */
237 	addi	r21, r0, _start
238 	addi	r22, r0, __end - 4 /* Include BSS too */
241 	or	r5, r0, r0
249 	add	r23, r0, r7 /* Move reloc addr to r23 */
250 	addi	r24, r0, CONFIG_SYS_TEXT_BASE /* Get reloc offset */
253 	addik	r6, r0, 0x2 /* BIG/LITTLE endian offset */
254 	lwi	r7, r0, 0x28
255 	swi	r6, r0, 0x28 /* used first unused MB vector */
256 	lbui	r10, r0, 0x28 /* used first unused MB vector */
257 	swi	r7, r0, 0x28
260 	addik	r6, r0, _exception_handler
262 	sw	r6, r1, r0
265 	sh	r7, r0, r8
267 	sh	r6, r0, r8
269 	addik	r6, r0, _hw_exception_handler
271 	sw	r6, r1, r0
274 	sh	r7, r0, r8
276 	sh	r6, r0, r8
278 	addik	r6, r0, _interrupt_handler
280 	sw	r6, r1, r0
283 	sh	r7, r0, r8
285 	sh	r6, r0, r8
297 3:	lw	r12, r21, r0 /* Load entry */
299 	sw	r12, r21, r0 /* Save entry back */
311 	addik	r5, r0, 0
312 	addik	r6, r0, XILINX_DCACHE_BYTE_SIZE
317 	addi	r6, r0, CONFIG_SYS_TEXT_BASE