Lines Matching +full:0 +full:x0c00
19 #define SCM_IPSBAR_BA(x) (((x)&0x03)<<30)
20 #define SCM_IPSBAR_V (0x00000001)
23 #define SCM_RAMBAR_BA(x) (((x)&0xFFFF)<<16)
24 #define SCM_RAMBAR_BDE (0x00000200)
27 #define SCM_CRSR_EXT (0x80)
30 #define SCM_CWCR_CWE (0x80)
31 #define SCM_CWCR_CWRI (0x40)
32 #define SCM_CWCR_CWT(x) (((x)&0x07)<<3)
33 #define SCM_CWCR_CWTA (0x04)
34 #define SCM_CWCR_CWTAVAL (0x02)
35 #define SCM_CWCR_CWTIC (0x01)
38 #define SCM_LPICR_ENBSTOP (0x80)
39 #define SCM_LPICR_XLPM_IPL(x) (((x)&0x07)<<4)
40 #define SCM_LPICR_XLPM_IPL_ANY (0x00)
41 #define SCM_LPICR_XLPM_IPL_L2_7 (0x10)
42 #define SCM_LPICR_XLPM_IPL_L3_7 (0x20)
43 #define SCM_LPICR_XLPM_IPL_L4_7 (0x30)
44 #define SCM_LPICR_XLPM_IPL_L5_7 (0x40)
45 #define SCM_LPICR_XLPM_IPL_L6_7 (0x50)
46 #define SCM_LPICR_XLPM_IPL_L7 (0x70)
49 #define SCM_DMAREQC_EXT(x) (((x)&0x0F)<<16)
50 #define SCM_DMAREQC_EXT_ETPU (0x00080000)
51 #define SCM_DMAREQC_EXT_EXTDREQ2 (0x00040000)
52 #define SCM_DMAREQC_EXT_EXTDREQ1 (0x00020000)
53 #define SCM_DMAREQC_EXT_EXTDREQ0 (0x00010000)
54 #define SCM_DMAREQC_DMAC3(x) (((x)&0x0F)<<12)
55 #define SCM_DMAREQC_DMAC2(x) (((x)&0x0F)<<8)
56 #define SCM_DMAREQC_DMAC1(x) (((x)&0x0F)<<4)
57 #define SCM_DMAREQC_DMAC0(x) (((x)&0x0F))
58 #define SCM_DMAREQC_DMACn_DTMR0 (0x04)
59 #define SCM_DMAREQC_DMACn_DTMR1 (0x05)
60 #define SCM_DMAREQC_DMACn_DTMR2 (0x06)
61 #define SCM_DMAREQC_DMACn_DTMR3 (0x07)
62 #define SCM_DMAREQC_DMACn_UART0RX (0x08)
63 #define SCM_DMAREQC_DMACn_UART1RX (0x09)
64 #define SCM_DMAREQC_DMACn_UART2RX (0x0A)
65 #define SCM_DMAREQC_DMACn_UART0TX (0x0C)
66 #define SCM_DMAREQC_DMACn_UART1TX (0x0D)
67 #define SCM_DMAREQC_DMACn_UART3TX (0x0E)
70 #define SCM_MPARK_M2_P_EN (0x02000000)
71 #define SCM_MPARK_M3_PRTY_MSK (0x00C00000)
72 #define SCM_MPARK_M3_PRTY_4TH (0x00000000)
73 #define SCM_MPARK_M3_PRTY_3RD (0x00400000)
74 #define SCM_MPARK_M3_PRTY_2ND (0x00800000)
75 #define SCM_MPARK_M3_PRTY_1ST (0x00C00000)
76 #define SCM_MPARK_M2_PRTY_MSK (0x00300000)
77 #define SCM_MPARK_M2_PRTY_4TH (0x00000000)
78 #define SCM_MPARK_M2_PRTY_3RD (0x00100000)
79 #define SCM_MPARK_M2_PRTY_2ND (0x00200000)
80 #define SCM_MPARK_M2_PRTY_1ST (0x00300000)
81 #define SCM_MPARK_M0_PRTY_MSK (0x000C0000)
82 #define SCM_MPARK_M0_PRTY_4TH (0x00000000)
83 #define SCM_MPARK_M0_PRTY_3RD (0x00040000)
84 #define SCM_MPARK_M0_PRTY_2ND (0x00080000)
85 #define SCM_MPARK_M0_PRTY_1ST (0x000C0000)
86 #define SCM_MPARK_FIXED (0x00004000)
87 #define SCM_MPARK_TIMEOUT (0x00002000)
88 #define SCM_MPARK_PRKLAST (0x00001000)
89 #define SCM_MPARK_LCKOUT_TIME(x) (((x)&0x0F)<<8)
92 #define SCM_MPR_MPR3 (0x08)
93 #define SCM_MPR_MPR2 (0x04)
94 #define SCM_MPR_MPR1 (0x02)
95 #define SCM_MPR_MPR0 (0x01)
98 #define SCM_PACRn_LOCK1 (0x80)
99 #define SCM_PACRn_ACCESSCTRL1(x) (((x)&0x07)<<4)
100 #define SCM_PACRn_LOCK0 (0x08)
101 #define SCM_PACRn_ACCESSCTRL0(x) (((x)&0x07))
104 #define SCM_PACRn_LOCK (0x80)
105 #define SCM_PACRn_ACCESSCTRL0(x) (((x)&0x07))
111 #define SDRAMC_DCR_NAM (0x2000)
112 #define SDRAMC_DCR_COC (0x1000)
113 #define SDRAMC_DCR_IS (0x0800)
114 #define SDRAMC_DCR_RTIM_MASK (0x0C00)
115 #define SDRAMC_DCR_RTIM_3CLKS (0x0000)
116 #define SDRAMC_DCR_RTIM_6CLKS (0x0200)
117 #define SDRAMC_DCR_RTIM_9CLKS (0x0400)
118 #define SDRAMC_DCR_RC(x) (((x)&0xFF)<<8)
121 #define SDRAMC_DARCn_BA(x) ((x)&0xFFFC0000)
122 #define SDRAMC_DARCn_RE (0x00008000)
123 #define SDRAMC_DARCn_CASL_MASK (0x00003000)
124 #define SDRAMC_DARCn_CASL_C0 (0x00000000)
125 #define SDRAMC_DARCn_CASL_C1 (0x00001000)
126 #define SDRAMC_DARCn_CASL_C2 (0x00002000)
127 #define SDRAMC_DARCn_CASL_C3 (0x00003000)
128 #define SDRAMC_DARCn_CBM_MASK (0x00000700)
129 #define SDRAMC_DARCn_CBM_CMD17 (0x00000000)
130 #define SDRAMC_DARCn_CBM_CMD18 (0x00000100)
131 #define SDRAMC_DARCn_CBM_CMD19 (0x00000200)
132 #define SDRAMC_DARCn_CBM_CMD20 (0x00000300)
133 #define SDRAMC_DARCn_CBM_CMD21 (0x00000400)
134 #define SDRAMC_DARCn_CBM_CMD22 (0x00000500)
135 #define SDRAMC_DARCn_CBM_CMD23 (0x00000600)
136 #define SDRAMC_DARCn_CBM_CMD24 (0x00000700)
137 #define SDRAMC_DARCn_IMRS (0x00000040)
138 #define SDRAMC_DARCn_PS_MASK (0x00000030)
139 #define SDRAMC_DARCn_PS_32 (0x00000000)
140 #define SDRAMC_DARCn_PS_16 (0x00000010)
141 #define SDRAMC_DARCn_PS_8 (0x00000020)
142 #define SDRAMC_DARCn_IP (0x00000008)
145 #define SDRAMC_DMRn_BAM(x) (((x)&0x3FFF)<<18)
146 #define SDRAMC_DMRn_WP (0x00000100)
147 #define SDRAMC_DMRn_V (0x00000001)
152 #define INT0_LO_RSVD0 (0)
215 /* 0 - 7 Reserved */
273 #define GPIO_PODR_ADDR(x) (((x)&0x07)<<5)
274 #define GPIO_PODR_ADDR_MASK (0xE0)
275 #define GPIO_PODR_BS(x) ((x)&0x0F)
276 #define GPIO_PODR_BS_MASK (0x0F)
277 #define GPIO_PODR_CS(x) (((x)&0x7F)<<1)
278 #define GPIO_PODR_CS_MASK (0xFE)
279 #define GPIO_PODR_SDRAM(X) ((x)&0x3F)
280 #define GPIO_PODR_SDRAM_MASK (0x3F)
283 #define GPIO_PODR_UARTH(x) ((x)&0x03)
284 #define GPIO_PODR_UARTH_MASK (0x03)
285 #define GPIO_PODR_QSPI(x) ((x)&0x1F)
286 #define GPIO_PODR_QSPI_MASK (0x1F)
287 #define GPIO_PODR_ETPU(x) ((x)&0x07)
288 #define GPIO_PODR_ETPU_MASK (0x07)
345 #define GPIO_PAR_AD_ADDR23 (0x80)
346 #define GPIO_PAR_AD_ADDR22 (0x40)
347 #define GPIO_PAR_AD_ADDR21 (0x20)
348 #define GPIO_PAR_AD_DATAL (0x01)
349 #define GPIO_PAR_BUSCTL_OE (0x4000)
350 #define GPIO_PAR_BUSCTL_TA (0x1000)
351 #define GPIO_PAR_BUSCTL_TEA(x) (((x)&0x03)<<10)
352 #define GPIO_PAR_BUSCTL_TEA_MASK (0x0C00)
353 #define GPIO_PAR_BUSCTL_TEA_GPIO (0x0400)
354 #define GPIO_PAR_BUSCTL_TEA_DREQ1 (0x0800)
355 #define GPIO_PAR_BUSCTL_TEA_EXTBUS (0x0C00)
356 #define GPIO_PAR_BUSCTL_RWB (0x0100)
357 #define GPIO_PAR_BUSCTL_TSIZ1 (0x0040)
358 #define GPIO_PAR_BUSCTL_TSIZ0 (0x0010)
359 #define GPIO_PAR_BUSCTL_TS(x) (((x)&0x03)<<2)
360 #define GPIO_PAR_BUSCTL_TS_MASK (0x0C)
361 #define GPIO_PAR_BUSCTL_TS_GPIO (0x04)
362 #define GPIO_PAR_BUSCTL_TS_DACK2 (0x08)
363 #define GPIO_PAR_BUSCTL_TS_EXTBUS (0x0C)
364 #define GPIO_PAR_BUSCTL_TIP(x) ((x)&0x03)
365 #define GPIO_PAR_BUSCTL_TIP_MASK (0x03)
366 #define GPIO_PAR_BUSCTL_TIP_GPIO (0x01)
367 #define GPIO_PAR_BUSCTL_TIP_DREQ0 (0x02)
368 #define GPIO_PAR_BUSCTL_TIP_EXTBUS (0x03)
369 #define GPIO_PAR_BS(x) ((x)&0x0F)
370 #define GPIO_PAR_BS_MASK (0x0F)
371 #define GPIO_PAR_CS(x) (((x)&0x7F)<<1)
372 #define GPIO_PAR_CS_MASK (0xFE)
373 #define GPIO_PAR_CS_CS7 (0x80)
374 #define GPIO_PAR_CS_CS6 (0x40)
375 #define GPIO_PAR_CS_CS5 (0x20)
376 #define GPIO_PAR_CS_CS4 (0x10)
377 #define GPIO_PAR_CS_CS3 (0x08)
378 #define GPIO_PAR_CS_CS2 (0x04)
379 #define GPIO_PAR_CS_CS1 (0x02)
382 #define GPIO_PAR_SDRAM_CSSDCS(x) (((x)&0x03)<<6)
383 #define GPIO_PAR_SDRAM_CSSDCS_MASK (0xC0)
384 #define GPIO_PAR_SDRAM_SDWE (0x20)
385 #define GPIO_PAR_SDRAM_SCAS (0x10)
386 #define GPIO_PAR_SDRAM_SRAS (0x08)
387 #define GPIO_PAR_SDRAM_SCKE (0x04)
388 #define GPIO_PAR_SDRAM_SDCS(x) ((x)&0x03)
389 #define GPIO_PAR_SDRAM_SDCS_MASK (0x03)
390 #define GPIO_PAR_FECI2C_EMDC(x) (((x)&0x03)<<6)
391 #define GPIO_PAR_FECI2C_EMDC_MASK (0xC0)
392 #define GPIO_PAR_FECI2C_EMDC_U2TXD (0x40)
393 #define GPIO_PAR_FECI2C_EMDC_I2CSCL (0x80)
394 #define GPIO_PAR_FECI2C_EMDC_FECEMDC (0xC0)
395 #define GPIO_PAR_FECI2C_EMDIO(x) (((x)&0x03)<<4)
396 #define GPIO_PAR_FECI2C_EMDIO_MASK (0x30)
397 #define GPIO_PAR_FECI2C_EMDIO_U2RXD (0x10)
398 #define GPIO_PAR_FECI2C_EMDIO_I2CSDA (0x20)
399 #define GPIO_PAR_FECI2C_EMDIO_FECEMDIO (0x30)
400 #define GPIO_PAR_FECI2C_SCL(x) (((x)&0x03)<<2)
401 #define GPIO_PAR_FECI2C_SCL_MASK (0x0C)
402 #define GPIO_PAR_FECI2C_SCL_CAN0RX (0x08)
403 #define GPIO_PAR_FECI2C_SCL_I2CSCL (0x0C)
404 #define GPIO_PAR_FECI2C_SDA(x) ((x)&0x03)
405 #define GPIO_PAR_FECI2C_SDA_MASK (0x03)
406 #define GPIO_PAR_FECI2C_SDA_CAN0TX (0x02)
407 #define GPIO_PAR_FECI2C_SDA_I2CSDA (0x03)
408 #define GPIO_PAR_UART_DREQ2 (0x8000)
409 #define GPIO_PAR_UART_CAN1EN (0x4000)
410 #define GPIO_PAR_UART_U2RXD (0x2000)
411 #define GPIO_PAR_UART_U2TXD (0x1000)
412 #define GPIO_PAR_UART_U1RXD(x) (((x)&0x03)<<10)
413 #define GPIO_PAR_UART_U1RXD_MASK (0x0C00)
414 #define GPIO_PAR_UART_U1RXD_CAN0RX (0x0800)
415 #define GPIO_PAR_UART_U1RXD_U1RXD (0x0C00)
416 #define GPIO_PAR_UART_U1TXD(x) (((x)&0x03)<<8)
417 #define GPIO_PAR_UART_U1TXD_MASK (0x0300)
418 #define GPIO_PAR_UART_U1TXD_CAN0TX (0x0200)
419 #define GPIO_PAR_UART_U1TXD_U1TXD (0x0300)
420 #define GPIO_PAR_UART_U1CTS(x) (((x)&0x03)<<6)
421 #define GPIO_PAR_UART_U1CTS_MASK (0x00C0)
422 #define GPIO_PAR_UART_U1CTS_U2CTS (0x0080)
423 #define GPIO_PAR_UART_U1CTS_U1CTS (0x00C0)
424 #define GPIO_PAR_UART_U1RTS(x) (((x)&0x03)<<4)
425 #define GPIO_PAR_UART_U1RTS_MASK (0x0030)
426 #define GPIO_PAR_UART_U1RTS_U2RTS (0x0020)
427 #define GPIO_PAR_UART_U1RTS_U1RTS (0x0030)
428 #define GPIO_PAR_UART_U0RXD (0x0008)
429 #define GPIO_PAR_UART_U0TXD (0x0004)
430 #define GPIO_PAR_UART_U0CTS (0x0002)
431 #define GPIO_PAR_UART_U0RTS (0x0001)
432 #define GPIO_PAR_QSPI_CS1(x) (((x)&0x03)<<6)
433 #define GPIO_PAR_QSPI_CS1_MASK (0xC0)
434 #define GPIO_PAR_QSPI_CS1_SDRAMSCKE (0x80)
435 #define GPIO_PAR_QSPI_CS1_QSPICS1 (0xC0)
436 #define GPIO_PAR_QSPI_CS0 (0x20)
437 #define GPIO_PAR_QSPI_DIN(x) (((x)&0x03)<<3)
438 #define GPIO_PAR_QSPI_DIN_MASK (0x18)
439 #define GPIO_PAR_QSPI_DIN_I2CSDA (0x10)
440 #define GPIO_PAR_QSPI_DIN_QSPIDIN (0x18)
441 #define GPIO_PAR_QSPI_DOUT (0x04)
442 #define GPIO_PAR_QSPI_SCK(x) ((x)&0x03)
443 #define GPIO_PAR_QSPI_SCK_MASK (0x03)
444 #define GPIO_PAR_QSPI_SCK_I2CSCL (0x02)
445 #define GPIO_PAR_QSPI_SCK_QSPISCK (0x03)
446 #define GPIO_PAR_DT3IN(x) (((x)&0x03)<<14)
447 #define GPIO_PAR_DT3IN_MASK (0xC000)
448 #define GPIO_PAR_DT3IN_QSPICS2 (0x4000)
449 #define GPIO_PAR_DT3IN_U2CTS (0x8000)
450 #define GPIO_PAR_DT3IN_DT3IN (0xC000)
451 #define GPIO_PAR_DT2IN(x) (((x)&0x03)<<12)
452 #define GPIO_PAR_DT2IN_MASK (0x3000)
453 #define GPIO_PAR_DT2IN_DT2OUT (0x1000)
454 #define GPIO_PAR_DT2IN_DREQ2 (0x2000)
455 #define GPIO_PAR_DT2IN_DT2IN (0x3000)
456 #define GPIO_PAR_DT1IN(x) (((x)&0x03)<<10)
457 #define GPIO_PAR_DT1IN_MASK (0x0C00)
458 #define GPIO_PAR_DT1IN_DT1OUT (0x0400)
459 #define GPIO_PAR_DT1IN_DREQ1 (0x0800)
460 #define GPIO_PAR_DT1IN_DT1IN (0x0C00)
461 #define GPIO_PAR_DT0IN(x) (((x)&0x03)<<8)
462 #define GPIO_PAR_DT0IN_MASK (0x0300)
463 #define GPIO_PAR_DT0IN_DREQ0 (0x0200)
464 #define GPIO_PAR_DT0IN_DT0IN (0x0300)
465 #define GPIO_PAR_DT3OUT(x) (((x)&0x03)<<6)
466 #define GPIO_PAR_DT3OUT_MASK (0x00C0)
467 #define GPIO_PAR_DT3OUT_QSPICS3 (0x0040)
468 #define GPIO_PAR_DT3OUT_U2RTS (0x0080)
469 #define GPIO_PAR_DT3OUT_DT3OUT (0x00C0)
470 #define GPIO_PAR_DT2OUT(x) (((x)&0x03)<<4)
471 #define GPIO_PAR_DT2OUT_MASK (0x0030)
472 #define GPIO_PAR_DT2OUT_DACK2 (0x0020)
473 #define GPIO_PAR_DT2OUT_DT2OUT (0x0030)
474 #define GPIO_PAR_DT1OUT(x) (((x)&0x03)<<2)
475 #define GPIO_PAR_DT1OUT_MASK (0x000C)
476 #define GPIO_PAR_DT1OUT_DACK1 (0x0008)
477 #define GPIO_PAR_DT1OUT_DT1OUT (0x000C)
478 #define GPIO_PAR_DT0OUT(x) ((x)&0x03)
479 #define GPIO_PAR_DT0OUT_MASK (0x0003)
480 #define GPIO_PAR_DT0OUT_DACK0 (0x0002)
481 #define GPIO_PAR_DT0OUT_DT0OUT (0x0003)
482 #define GPIO_PAR_ETPU_TCRCLK (0x04)
483 #define GPIO_PAR_ETPU_UTPU_ODIS (0x02)
484 #define GPIO_PAR_ETPU_LTPU_ODIS (0x01)
487 #define GPIO_DSCR_EIM_EIM1 (0x10)
488 #define GPIO_DSCR_EIM_EIM0 (0x01)
489 #define GPIO_DSCR_ETPU_ETPU31_24 (0x40)
490 #define GPIO_DSCR_ETPU_ETPU23_16 (0x10)
491 #define GPIO_DSCR_ETPU_ETPU15_8 (0x04)
492 #define GPIO_DSCR_ETPU_ETPU7_0 (0x01)
493 #define GPIO_DSCR_FECI2C_FEC (0x10)
494 #define GPIO_DSCR_FECI2C_I2C (0x01)
495 #define GPIO_DSCR_UART_IRQ (0x40)
496 #define GPIO_DSCR_UART_UART2 (0x10)
497 #define GPIO_DSCR_UART_UART1 (0x04)
498 #define GPIO_DSCR_UART_UART0 (0x01)
499 #define GPIO_DSCR_QSPI_QSPI (0x01)
500 #define GPIO_DSCR_TIMER (0x01)
506 #define CCM_RCR_SOFTRST (0x80)
507 #define CCM_RCR_FRCRSTOUT (0x40)
510 #define CCM_RSR_SOFT (0x20)
511 #define CCM_RSR_WDR (0x10)
512 #define CCM_RSR_POR (0x08)
513 #define CCM_RSR_EXT (0x04)
514 #define CCM_RSR_LOC (0x02)
515 #define CCM_RSR_LOL (0x01)
518 #define CCM_CCR_LOAD (0x8000)
519 #define CCM_CCR_SZEN (0x0040)
520 #define CCM_CCR_PSTEN (0x0020)
521 #define CCM_CCR_BME (0x0008)
522 #define CCM_CCR_BMT(x) ((x)&0x07)
523 #define CCM_CCR_BMT_MASK (0x0007)
524 #define CCM_CCR_BMT_64K (0x0000)
525 #define CCM_CCR_BMT_32K (0x0001)
526 #define CCM_CCR_BMT_16K (0x0002)
527 #define CCM_CCR_BMT_8K (0x0003)
528 #define CCM_CCR_BMT_4K (0x0004)
529 #define CCM_CCR_BMT_2K (0x0005)
530 #define CCM_CCR_BMT_1K (0x0006)
531 #define CCM_CCR_BMT_512 (0x0007)
534 #define CCM_RCON_RCSC(x) (((x)&0x0003)<<8)
535 #define CCM_RCON_RLOAD (0x0020)
536 #define CCM_RCON_BOOTPS(x) (((x)&0x0003)<<3)
537 #define CCM_RCON_BOOTPS_MASK (0x0018)
538 #define CCM_RCON_BOOTPS_32 (0x0018)
539 #define CCM_RCON_BOOTPS_16 (0x0008)
540 #define CCM_RCON_BOOTPS_8 (0x0010)
541 #define CCM_RCON_MODE (0x0001)
544 #define CCM_CIR_PIN(x) (((x) & 0xFFC0) >> 6)
545 #define CCM_CIR_PRN(x) ((x) & 0x003F)
551 #define PLL_SYNCR_MFD(x) (((x)&0x07)<<24)
552 #define PLL_SYNCR_MFD_MASK (0x07000000)
553 #define PLL_SYNCR_RFC(x) (((x)&0x07)<<19)
554 #define PLL_SYNCR_RFC_MASK (0x00380000)
555 #define PLL_SYNCR_LOCEN (0x00040000)
556 #define PLL_SYNCR_LOLRE (0x00020000)
557 #define PLL_SYNCR_LOCRE (0x00010000)
558 #define PLL_SYNCR_DISCLK (0x00008000)
559 #define PLL_SYNCR_LOLIRQ (0x00004000)
560 #define PLL_SYNCR_LOCIRQ (0x00002000)
561 #define PLL_SYNCR_RATE (0x00001000)
562 #define PLL_SYNCR_DEPTH(x) (((x)&0x03)<<10)
563 #define PLL_SYNCR_EXP(x) ((x)&0x03FF)
566 #define PLL_SYNSR_LOLF (0x00000200)
567 #define PLL_SYNSR_LOC (0x00000100)
568 #define PLL_SYNSR_MODE (0x00000080)
569 #define PLL_SYNSR_PLLSEL (0x00000040)
570 #define PLL_SYNSR_PLLREF (0x00000020)
571 #define PLL_SYNSR_LOCKS (0x00000010)
572 #define PLL_SYNSR_LOCK (0x00000008)
573 #define PLL_SYNSR_LOCF (0x00000004)
574 #define PLL_SYNSR_CALDONE (0x00000002)
575 #define PLL_SYNSR_CALPASS (0x00000001)
581 #define WTM_WCR_WAIT (0x0008)
582 #define WTM_WCR_DOZE (0x0004)
583 #define WTM_WCR_HALTED (0x0002)
584 #define WTM_WCR_EN (0x0001)