include/asm/m5227x.h

4  * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
5  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7  * SPDX-License-Identifier:	GPL-2.0+
136 #define CCM_MISCCR_USBPUE		(0x2000)	/* USB transceiver pull-up */
154 #define CCM_MISCCR_USBOC		(0x0002)	/* USB VBUS over-current sense pol */
163 #define CCM_UOCSR_DPPD			(0x2000)	/* D+ 15Kohm pull-down (rd-only) */
164 #define CCM_UOCSR_DMPD			(0x1000)	/* D- 15Kohm pull-down (rd-only) */
165 #define CCM_UOCSR_CRG_VBUS		(0x0400)	/* VBUS charge resistor enabled (rd-only) */
166 #define CCM_UOCSR_DCR_VBUS		(0x0200)	/* VBUS discharge resistor en (rd-only) */
167 #define CCM_UOCSR_DPPU			(0x0100)	/* D+ pull-up for FS enabled (rd-only) */
168 #define CCM_UOCSR_AVLD			(0x0080)	/* A-peripheral valid indicator */
169 #define CCM_UOCSR_BVLD			(0x0040)	/* B-peripheral valid indicator */
170 #define CCM_UOCSR_VVLD			(0x0020)	/* VBUS valid indicator */
172 #define CCM_UOCSR_WKUP			(0x0004)	/* USB OTG controller wake-up event */
174 #define CCM_UOCSR_XPDE			(0x0001)	/* On-chip transceiver pull-down en */
474 #define SDRAMC_SDCR_DPD			(0x00000001)	/* Deep Power-Down Mode */
505 #define SDRAMC_SDCS_CSSZ(x)		(((x)&0x0000001F))	/* Chip-Select Size */
506 #define SDRAMC_SDCS_CSBA(x)		(((x)&0x00000FFF)<<20)	/* Chip-Select Base Address */
528 #define PLL_PCR_OUTDIV1(x)		(((x)&0x0000000F))	/* Output divider for CPU clock frequency */
529 #define PLL_PCR_OUTDIV2(x)		(((x)&0x0000000F)<<4)	/* Output divider for bus/flexbus clock frequency…
530 #define PLL_PCR_OUTDIV3(x)		(((x)&0x0000000F)<<8)	/* Output divider for SDRAM clock frequency */
531 #define PLL_PCR_OUTDIV5(x)		(((x)&0x0000000F)<<16)	/* Output divider for USB clock frequency */
532 #define PLL_PCR_PFDR(x)			(((x)&0x000000FF)<<24)	/* Feedback divider for VCO frequency */
540 #define PLL_PSR_LOCKS			(0x00000001)	/* PLL lost lock - sticky */
542 #define PLL_PSR_LOLIRQ			(0x00000004)	/* PLL loss-of-lock interrupt enable */
543 #define PLL_PSR_LOLRE			(0x00000008)	/* PLL loss-of-lock reset enable */