44 #warning "Chip Select 0 are not initialized/used"  in init_fbcs()
100 	out_be16(&wdg->cr, 0);  in cpu_init_f()
103 	out_be32(&scm1->mpr, 0x77777777);  in cpu_init_f()
104 	out_be32(&scm1->pacra, 0);  in cpu_init_f()
105 	out_be32(&scm1->pacrb, 0);  in cpu_init_f()
106 	out_be32(&scm1->pacrc, 0);  in cpu_init_f()
107 	out_be32(&scm1->pacrd, 0);  in cpu_init_f()
108 	out_be32(&scm1->pacre, 0);  in cpu_init_f()
109 	out_be32(&scm1->pacrf, 0);  in cpu_init_f()
120 	return (0);  in cpu_init_r()
129 	case 0:  in uart_port_conf()
175 	return 0;  in fecpin_setclear()
190 	mbar_writeByte(MCFSIM_MPARK, 0x40);	/* 5249 Internal Core takes priority over DMA */  in cpu_init_f()
191 	mbar_writeByte(MCFSIM_SYPCR, 0x00);  in cpu_init_f()
192 	mbar_writeByte(MCFSIM_SWIVR, 0x0f);  in cpu_init_f()
193 	mbar_writeByte(MCFSIM_SWSR, 0x00);  in cpu_init_f()
194 	mbar_writeByte(MCFSIM_SWDICR, 0x00);  in cpu_init_f()
195 	mbar_writeByte(MCFSIM_TIMER1ICR, 0x00);  in cpu_init_f()
196 	mbar_writeByte(MCFSIM_TIMER2ICR, 0x88);  in cpu_init_f()
197 	mbar_writeByte(MCFSIM_I2CICR, 0x00);  in cpu_init_f()
198 	mbar_writeByte(MCFSIM_UART1ICR, 0x00);  in cpu_init_f()
199 	mbar_writeByte(MCFSIM_UART2ICR, 0x00);  in cpu_init_f()
200 	mbar_writeByte(MCFSIM_ICR6, 0x00);  in cpu_init_f()
201 	mbar_writeByte(MCFSIM_ICR7, 0x00);  in cpu_init_f()
202 	mbar_writeByte(MCFSIM_ICR8, 0x00);  in cpu_init_f()
203 	mbar_writeByte(MCFSIM_ICR9, 0x00);  in cpu_init_f()
204 	mbar_writeByte(MCFSIM_QSPIICR, 0x00);  in cpu_init_f()
206 	mbar2_writeLong(MCFSIM_GPIO_INT_EN, 0x00000080);  in cpu_init_f()
207 	mbar2_writeByte(MCFSIM_INTBASE, 0x40);	/* Base interrupts at 64 */  in cpu_init_f()
208 	mbar2_writeByte(MCFSIM_SPURVEC, 0x00);  in cpu_init_f()
210 	/*mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); */ /* Enable a 1 cycle pre-drive cycle on CS1 */  in cpu_init_f()
232 	return (0);  in cpu_init_r()
242 		clrbits_be32(par, 0x00180000);  in uart_port_conf()
243 		setbits_be32(par, 0x00180000);  in uart_port_conf()
246 		clrbits_be32(par, 0x00000003);  in uart_port_conf()
247 		clrbits_be32(par, 0xFFFFFFFC);  in uart_port_conf()
258 	mbar_writeShort(MCF_WTM_WCR, 0);  in cpu_init_f()
270 			MCF_FMPLL_SYNCR_MFD(0) | MCF_FMPLL_SYNCR_RFD(0));  in cpu_init_f()
280 	return (0);  in cpu_init_r()
289 	case 0:  in uart_port_conf()
290 		temp = mbar_readShort(MCF_GPIO_PAR_UART) & 0xFFF3;  in uart_port_conf()
295 		temp = mbar_readShort(MCF_GPIO_PAR_UART) & 0xF0FF;  in uart_port_conf()
300 		temp = mbar_readShort(MCF_GPIO_PAR_UART) & 0xCFFF;  in uart_port_conf()
301 		temp |= (0x3000);  in uart_port_conf()
313 			       (mbar_readByte(MCF_GPIO_PAR_FECI2C) | 0xF0));  in fecpin_setclear()
317 	return 0;  in fecpin_setclear()
404 	return (0);  in cpu_init_r()
413 	case 0:  in uart_port_conf()
441 	return 0;  in fecpin_setclear()
467 	out_be16(&wdog_reg->wcr, 0);  in cpu_init_f()
487 	return (0);  in cpu_init_r()
496 	case 0:  in uart_port_conf()
520 			setbits_be16(&gpio->par_feci2c, 0x0f00);  in fecpin_setclear()
521 			setbits_8(&gpio->par_fec0hl, 0xc0);  in fecpin_setclear()
523 			setbits_be16(&gpio->par_feci2c, 0x00a0);  in fecpin_setclear()
524 			setbits_8(&gpio->par_fec1hl, 0xc0);  in fecpin_setclear()
528 			clrbits_be16(&gpio->par_feci2c, 0x0f00);  in fecpin_setclear()
529 			clrbits_8(&gpio->par_fec0hl, 0xc0);  in fecpin_setclear()
531 			clrbits_be16(&gpio->par_feci2c, 0x00a0);  in fecpin_setclear()
532 			clrbits_8(&gpio->par_fec1hl, 0xc0);  in fecpin_setclear()
536 	return 0;  in fecpin_setclear()
553 	MCFWTM_WCR = 0;  in cpu_init_f()
563 	MCFGPIO_PBCDPAR = 0xc0;  in cpu_init_f()
624 	return (0);  in cpu_init_r()
631 	case 0:  in uart_port_conf()
632 		MCFGPIO_PUAPAR &= 0xFc;  in uart_port_conf()
633 		MCFGPIO_PUAPAR |= 0x03;  in uart_port_conf()
636 		MCFGPIO_PUAPAR &= 0xF3;  in uart_port_conf()
637 		MCFGPIO_PUAPAR |= 0x0C;  in uart_port_conf()
640 		MCFGPIO_PASPAR &= 0xFF0F;  in uart_port_conf()
641 		MCFGPIO_PASPAR |= 0x00A0;  in uart_port_conf()
650 		MCFGPIO_PASPAR |= 0x0F00;  in fecpin_setclear()
653 		MCFGPIO_PASPAR &= 0xF0FF;  in fecpin_setclear()
656 	return 0;  in fecpin_setclear()
691 	mbar_writeByte(MCFSIM_MPARK, 0x30);	/* 5249 Internal Core takes priority over DMA */  in cpu_init_f()
692 	mbar_writeByte(MCFSIM_SYPCR, 0x00);  in cpu_init_f()
693 	mbar_writeByte(MCFSIM_SWIVR, 0x0f);  in cpu_init_f()
694 	mbar_writeByte(MCFSIM_SWSR, 0x00);  in cpu_init_f()
695 	mbar_writeLong(MCFSIM_IMR, 0xfffffbff);  in cpu_init_f()
696 	mbar_writeByte(MCFSIM_SWDICR, 0x00);  in cpu_init_f()
697 	mbar_writeByte(MCFSIM_TIMER1ICR, 0x00);  in cpu_init_f()
698 	mbar_writeByte(MCFSIM_TIMER2ICR, 0x88);  in cpu_init_f()
699 	mbar_writeByte(MCFSIM_I2CICR, 0x00);  in cpu_init_f()
700 	mbar_writeByte(MCFSIM_UART1ICR, 0x00);  in cpu_init_f()
701 	mbar_writeByte(MCFSIM_UART2ICR, 0x00);  in cpu_init_f()
702 	mbar_writeByte(MCFSIM_ICR6, 0x00);  in cpu_init_f()
703 	mbar_writeByte(MCFSIM_ICR7, 0x00);  in cpu_init_f()
704 	mbar_writeByte(MCFSIM_ICR8, 0x00);  in cpu_init_f()
705 	mbar_writeByte(MCFSIM_ICR9, 0x00);  in cpu_init_f()
706 	mbar_writeByte(MCFSIM_QSPIICR, 0x00);  in cpu_init_f()
708 	mbar2_writeLong(MCFSIM_GPIO_INT_EN, 0x00000080);  in cpu_init_f()
709 	mbar2_writeByte(MCFSIM_INTBASE, 0x40);	/* Base interrupts at 64 */  in cpu_init_f()
710 	mbar2_writeByte(MCFSIM_SPURVEC, 0x00);  in cpu_init_f()
711 	mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020);	/* Enable a 1 cycle pre-drive cycle on CS1 */  in cpu_init_f()
714 	/* mbar2_writeLong(MCFSIM_INTLEV5, 0x70000000); */  in cpu_init_f()
717 	mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020);  in cpu_init_f()
718 	mbar2_writeLong(MCFSIM_IDECONFIG2, 0x00000000);  in cpu_init_f()
732 	return (0);  in cpu_init_r()