Lines Matching refs:move
17 move.w #0x2700,%sr; /* disable intrs */ \
109 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
112 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
116 move.l #0xFC008000, %a1
117 move.l #(CONFIG_SYS_CS0_BASE), (%a1)
118 move.l #0xFC008008, %a1
119 move.l #(CONFIG_SYS_CS0_CTRL), (%a1)
120 move.l #0xFC008004, %a1
121 move.l #(CONFIG_SYS_CS0_MASK), (%a1)
127 move.l #0xFC0A4074, %a1
128 move.b #(CONFIG_SYS_SDRAM_DRV_STRENGTH), (%a1)
132 move.l #0xFC0B8110, %a1
133 move.l #0xFC0B8114, %a2
136 move.l #0x13, %d1
137 move.l #(CONFIG_SYS_SDRAM_SIZE), %d2
149 move.l #(CONFIG_SYS_SDRAM_BASE), (%a1)
152 move.l #(CONFIG_SYS_SDRAM_BASE1), (%a2)
158 move.l #0xFC0B8008, %a1
159 move.l #(CONFIG_SYS_SDRAM_CFG1), (%a1)
161 move.l #0xFC0B800C, %a2
162 move.l #(CONFIG_SYS_SDRAM_CFG2), (%a2)
165 move.l #0xFC0B8000, %a1 /* Mode */
166 move.l #0xFC0B8004, %a2 /* Ctrl */
169 move.l #(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
173 move.l #(CONFIG_SYS_SDRAM_MODE), (%a1)
175 move.l #(CONFIG_SYS_SDRAM_EMOD), (%a1)
178 move.l #1000, %d0
185 move.l #(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
189 move.l #(CONFIG_SYS_SDRAM_CTRL + 4), %d0
191 move.l %d0, (%a2)
192 move.l %d0, (%a2)
195 move.l #(CONFIG_SYS_SDRAM_CTRL), %d0
198 move.l %d0, (%a2)
211 move.l #0xFC0A4036, %a0
212 move.b #0x3F, %d0
213 move.b %d0, (%a0)
217 move.b (%a0), %d0
219 move.b %d0, (%a0)
222 move.l #0xFC0A4037, %a0
223 move.b (%a0), %d0
225 move.b %d0, (%a0)
230 move.l #0xFC05C000, %a0
231 move.l #0x80FF0C00, (%a0) /* Master, clear TX/RX FIFO */
233 move.l #0xFC05C00C, %a0
234 move.l #0x3E000011, (%a0)
236 move.l #0xFC05C034, %a2 /* dtfr */
237 move.l #0xFC05C03B, %a3 /* drfr */
239 move.l #(ASM_SBF_IMG_HDR + 4), %a1
240 move.l (%a1)+, %d5
241 move.l (%a1), %a4
243 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_SBFHDR_DATA_OFFSET), %a0
244 move.l #(CONFIG_SYS_SBFHDR_SIZE), %d4
246 move.l #0xFC05C02C, %a1 /* dspi status */
249 move.l #0x8004000B, %d2 /* Fast Read Cmd */
253 move.l #0x80040000, %d2 /* Address byte 2 */
257 move.l #0x80040000, %d2 /* Address byte 1 */
261 move.l #0x80040000, %d2 /* Address byte 0 */
265 move.l #0x80040000, %d2 /* Dummy Wr and Rd */
271 move.l #0x80040000, %d2
275 move.b %d1, (%a0) /* read, copy to dst */
283 move.l #0x80040000, %d2
287 move.b %d1, (%a4) /* read, copy to dst */
293 move.l #0x00040000, %d2 /* Terminate */
298 move.l #(CONFIG_SYS_TEXT_BASE + 0x400), %a0
299 move.l %a0, (%a1)
303 move.l (%a1), %d0 /* status */
308 move.l %d2, (%a2)
312 move.l (%a1), %d0 /* status */
318 move.b (%a3), %d1
328 move.w #0x2700,%sr /* Mask off Interrupt */
332 move.l #CONFIG_SYS_TEXT_BASE, %d0
335 move.l #CONFIG_SYS_FLASH_BASE, %d0
338 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
343 move.l #CF_CACR_CINV, %d0 /* Invalidate cache cmd */
345 move.l #0, %d0
350 move.l #0, %d0
351 move.l #(ICACHE_STATUS), %a1 /* icache */
352 move.l #(DCACHE_STATUS), %a2 /* icache */
353 move.l %d0, (%a1)
354 move.l %d0, (%a2)
357 move.l #__got_start, %a5
360 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp
366 move.l %sp, -(%sp)
370 move.l %d0, %sp
371 move.l %sp, %fp
374 move.l %d0, -(%sp)
402 move.l 8(%a6), %sp /* set new stack pointer */
404 move.l 12(%a6), %d0 /* Save copy of Global Data pointer */
405 move.l 16(%a6), %a0 /* Save copy of Destination Address */
407 move.l #CONFIG_SYS_MONITOR_BASE, %a1
408 move.l #__init_end, %a2
409 move.l %a0, %a3
413 move.l (%a1)+, (%a3)+
421 move.l %a0, %a1
431 move.l %a0, %a1
433 move.l %a0, %d1
443 move.l %a0, %a1
445 move.l %a1,%a5 /* fix got pointer register a5 */
447 move.l %a0, %a2
451 move.l (%a1),%d1
454 move.l %d1,(%a1)+
459 move.l %a0, %a1
463 move.l %a0,-(%sp) /* dest_addr */
464 move.l %d0,-(%sp) /* gd */