Lines Matching +full:0 +full:x80040000

17 	move.w	#0x2700,%sr;		/* disable intrs */	\
41 INITSP:	.long	0			/* Initial SP	*/
44 INITSP:	.long	0			/* Initial SP	*/
60 /* TRAP #0 - #15 */
104 	.long	0x00000000		/* checksum, not yet implemented */
105 	.long	0x00020000		/* image length */
116 	move.l	#0xFC008000, %a1
118 	move.l	#0xFC008008, %a1
120 	move.l	#0xFC008004, %a1
127 	move.l	#0xFC0A4074, %a1
131 	/* SDRAM Chip 0 and 1 */
132 	move.l	#0xFC0B8110, %a1
133 	move.l	#0xFC0B8114, %a2
136 	move.l	#0x13, %d1
148 	/* SDRAM Chip 0 and 1 */
158 	move.l	#0xFC0B8008, %a1
161 	move.l	#0xFC0B800C, %a2
165 	move.l	#0xFC0B8000, %a1	/* Mode */
166 	move.l	#0xFC0B8004, %a2	/* Ctrl */
196 	and.l	#0x7FFFFFFF, %d0
197 	or.l	#0x10000c00, %d0
203 	 * a0 - general, sram - 0x80008000 - 32, see M52277EVB.h
211 	move.l	#0xFC0A4036, %a0
212 	move.b	#0x3F, %d0
218 	or.l	#0xC0, %d0
222 	move.l	#0xFC0A4037, %a0
224 	or.l	#0x10, %d0
230 	move.l	#0xFC05C000, %a0
231 	move.l	#0x80FF0C00, (%a0)	/* Master, clear TX/RX FIFO */
233 	move.l	#0xFC05C00C, %a0
234 	move.l	#0x3E000011, (%a0)
236 	move.l	#0xFC05C034, %a2	/* dtfr */
237 	move.l	#0xFC05C03B, %a3	/* drfr */
246 	move.l	#0xFC05C02C, %a1	/* dspi status */
249 	move.l	#0x8004000B, %d2	/* Fast Read Cmd */
253 	move.l	#0x80040000, %d2	/* Address byte 2 */
257 	move.l	#0x80040000, %d2	/* Address byte 1 */
261 	move.l	#0x80040000, %d2	/* Address byte 0 */
265 	move.l	#0x80040000, %d2	/* Dummy Wr and Rd */
271 	move.l	#0x80040000, %d2
283 	move.l	#0x80040000, %d2
293 	move.l	#0x00040000, %d2	/* Terminate */
298 	move.l	#(CONFIG_SYS_TEXT_BASE + 0x400), %a0
304 	and.l	#0x0000F000, %d0
305 	cmp.l	#0x00003000, %d0
313 	and.l	#0x000000F0, %d0
315 	cmp.l	#0, %d0
323 	. = 0x400
328 	move.w	#0x2700,%sr		/* Mask off Interrupt */
345 	move.l	#0, %d0
350 	move.l	#0, %d0
401 	link.w	%a6,#0
494 .ascii U_BOOT_VERSION_STRING, "\0"