34 static u32 umc_cmdctla[DRAM_FREQ_NR] = {0x55990b11, 0x66bb0f17};
35 static u32 umc_cmdctla_plus[DRAM_FREQ_NR] = {0x45990b11, 0x46bb0f17};
36 static u32 umc_cmdctlb[DRAM_FREQ_NR] = {0x16958944, 0x18c6ab44};
37 static u32 umc_cmdctlb_plus[DRAM_FREQ_NR] = {0x16958924, 0x18c6ab24};
39 	{0x00240512, 0x00350512, 0x00000000}, /* no data for 1333MHz,128MB */
40 	{0x002b0617, 0x003f0617, 0x00670617},
42 static u32 umc_spcctlb[DRAM_FREQ_NR] = {0x00ff0006, 0x00ff0008};
43 static u32 umc_rdatactl[DRAM_FREQ_NR] = {0x000a00ac, 0x000c00ac};
52 	writel(0x00000000, ssif_base + 0x0000b004);  in umc_start_ssif()
53 	writel(0xffffffff, ssif_base + 0x0000c004);  in umc_start_ssif()
54 	writel(0x000fffcf, ssif_base + 0x0000c008);  in umc_start_ssif()
55 	writel(0x00000001, ssif_base + 0x0000b000);  in umc_start_ssif()
56 	writel(0x00000001, ssif_base + 0x0000c000);  in umc_start_ssif()
57 	writel(0x03010101, ssif_base + UMC_MDMCHSEL);  in umc_start_ssif()
58 	writel(0x03010100, ssif_base + UMC_DMDCHSEL);  in umc_start_ssif()
60 	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_FETCH);  in umc_start_ssif()
61 	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE0);  in umc_start_ssif()
62 	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC0);  in umc_start_ssif()
63 	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC0);  in umc_start_ssif()
64 	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE1);  in umc_start_ssif()
65 	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC1);  in umc_start_ssif()
66 	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC1);  in umc_start_ssif()
67 	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_WC);  in umc_start_ssif()
68 	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_RC);  in umc_start_ssif()
69 	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_DST);  in umc_start_ssif()
71 	writel(0x00000001, ssif_base + UMC_CPURST);  in umc_start_ssif()
72 	writel(0x00000001, ssif_base + UMC_IDSRST);  in umc_start_ssif()
73 	writel(0x00000001, ssif_base + UMC_IXMRST);  in umc_start_ssif()
74 	writel(0x00000001, ssif_base + UMC_MDMRST);  in umc_start_ssif()
75 	writel(0x00000001, ssif_base + UMC_MDDRST);  in umc_start_ssif()
76 	writel(0x00000001, ssif_base + UMC_SIORST);  in umc_start_ssif()
77 	writel(0x00000001, ssif_base + UMC_VIORST);  in umc_start_ssif()
78 	writel(0x00000001, ssif_base + UMC_FRCRST);  in umc_start_ssif()
79 	writel(0x00000001, ssif_base + UMC_RGLRST);  in umc_start_ssif()
80 	writel(0x00000001, ssif_base + UMC_AIORST);  in umc_start_ssif()
81 	writel(0x00000001, ssif_base + UMC_DMDRST);  in umc_start_ssif()
103 	case 0:  in umc_dramcont_init()
104 		return 0;  in umc_dramcont_init()
115 		pr_err("unsupported DRAM size 0x%08lx\n", size);  in umc_dramcont_init()
126 	writel(0x04060806, dc_base + UMC_WDATACTL_D0);  in umc_dramcont_init()
127 	writel(0x04a02000, dc_base + UMC_DATASET);  in umc_dramcont_init()
128 	writel(0x00000000, ca_base + 0x2300);  in umc_dramcont_init()
129 	writel(0x00400020, dc_base + UMC_DCCGCTL);  in umc_dramcont_init()
130 	writel(0x00000003, dc_base + 0x7000);  in umc_dramcont_init()
131 	writel(0x0000004f, dc_base + 0x8000);  in umc_dramcont_init()
132 	writel(0x000000c3, dc_base + 0x8004);  in umc_dramcont_init()
133 	writel(0x00000077, dc_base + 0x8008);  in umc_dramcont_init()
134 	writel(0x0000003b, dc_base + UMC_DICGCTLA);  in umc_dramcont_init()
135 	writel(0x020a0808, dc_base + UMC_DICGCTLB);  in umc_dramcont_init()
136 	writel(0x00000004, dc_base + UMC_FLOWCTLG);  in umc_dramcont_init()
137 	writel(0x80000201, ca_base + 0xc20);  in umc_dramcont_init()
138 	writel(0x0801e01e, dc_base + UMC_FLOWCTLA);  in umc_dramcont_init()
139 	writel(0x00200000, dc_base + UMC_FLOWCTLB);  in umc_dramcont_init()
140 	writel(0x00004444, dc_base + UMC_FLOWCTLC);  in umc_dramcont_init()
141 	writel(0x200a0a00, dc_base + UMC_SPCSETB);  in umc_dramcont_init()
142 	writel(0x00000000, dc_base + UMC_SPCSETD);  in umc_dramcont_init()
143 	writel(0x00000520, dc_base + UMC_DFICUPDCTLA);  in umc_dramcont_init()
145 	return 0;  in umc_dramcont_init()
151 	void __iomem *phy_base = dc_base + 0x00001000;  in umc_ch_init()
158 	writel(0x00000101, dc_base + UMC_DIOCTLA);  in umc_ch_init()
174 	void __iomem *umc_base = (void __iomem *)0x5b800000;  in uniphier_sld8_umc_init()
175 	void __iomem *ca_base = umc_base + 0x00001000;  in uniphier_sld8_umc_init()
176 	void __iomem *dc_base = umc_base + 0x00400000;  in uniphier_sld8_umc_init()
180 	for (ch = 0; ch < DRAM_CH_NR; ch++) {  in uniphier_sld8_umc_init()
189 		ca_base += 0x00001000;  in uniphier_sld8_umc_init()
190 		dc_base += 0x00200000;  in uniphier_sld8_umc_init()
195 	return 0;  in uniphier_sld8_umc_init()