28 static u32 umc_spcctla[DRAM_SZ_NR] = {0x002b0617, 0x003f0617, 0x00770617};
32 	writel(0x00000000, ssif_base + 0x0000b004);  in umc_start_ssif()
33 	writel(0xffffffff, ssif_base + 0x0000c004);  in umc_start_ssif()
34 	writel(0x000fffcf, ssif_base + 0x0000c008);  in umc_start_ssif()
35 	writel(0x00000001, ssif_base + 0x0000b000);  in umc_start_ssif()
36 	writel(0x00000001, ssif_base + 0x0000c000);  in umc_start_ssif()
38 	writel(0x03010100, ssif_base + UMC_HDMCHSEL);  in umc_start_ssif()
39 	writel(0x03010101, ssif_base + UMC_MDMCHSEL);  in umc_start_ssif()
40 	writel(0x03010100, ssif_base + UMC_DVCCHSEL);  in umc_start_ssif()
41 	writel(0x03010100, ssif_base + UMC_DMDCHSEL);  in umc_start_ssif()
43 	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_FETCH);  in umc_start_ssif()
44 	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE0);  in umc_start_ssif()
45 	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC0);  in umc_start_ssif()
46 	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC0);  in umc_start_ssif()
47 	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE1);  in umc_start_ssif()
48 	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC1);  in umc_start_ssif()
49 	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC1);  in umc_start_ssif()
50 	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_WC);  in umc_start_ssif()
51 	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_RC);  in umc_start_ssif()
52 	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_DST);  in umc_start_ssif()
53 	writel(0x00000000, ssif_base + 0x0000c044);		/* DCGIV_SSIF_REG */  in umc_start_ssif()
55 	writel(0x00000001, ssif_base + UMC_CPURST);  in umc_start_ssif()
56 	writel(0x00000001, ssif_base + UMC_IDSRST);  in umc_start_ssif()
57 	writel(0x00000001, ssif_base + UMC_IXMRST);  in umc_start_ssif()
58 	writel(0x00000001, ssif_base + UMC_HDMRST);  in umc_start_ssif()
59 	writel(0x00000001, ssif_base + UMC_MDMRST);  in umc_start_ssif()
60 	writel(0x00000001, ssif_base + UMC_HDDRST);  in umc_start_ssif()
61 	writel(0x00000001, ssif_base + UMC_MDDRST);  in umc_start_ssif()
62 	writel(0x00000001, ssif_base + UMC_SIORST);  in umc_start_ssif()
63 	writel(0x00000001, ssif_base + UMC_GIORST);  in umc_start_ssif()
64 	writel(0x00000001, ssif_base + UMC_HD2RST);  in umc_start_ssif()
65 	writel(0x00000001, ssif_base + UMC_VIORST);  in umc_start_ssif()
66 	writel(0x00000001, ssif_base + UMC_DVCRST);  in umc_start_ssif()
67 	writel(0x00000001, ssif_base + UMC_RGLRST);  in umc_start_ssif()
68 	writel(0x00000001, ssif_base + UMC_VPERST);  in umc_start_ssif()
69 	writel(0x00000001, ssif_base + UMC_AIORST);  in umc_start_ssif()
70 	writel(0x00000001, ssif_base + UMC_DMDRST);  in umc_start_ssif()
99 		pr_err("unsupported DRAM size 0x%08lx (per 16bit)\n", size);  in umc_dramcont_init()
103 	writel(0x66bb0f17, dc_base + UMC_CMDCTLA);  in umc_dramcont_init()
104 	writel(0x18c6aa44, dc_base + UMC_CMDCTLB);  in umc_dramcont_init()
106 	writel(0x00ff0008, dc_base + UMC_SPCCTLB);  in umc_dramcont_init()
107 	writel(0x000c00ae, dc_base + UMC_RDATACTL_D0);  in umc_dramcont_init()
108 	writel(0x000c00ae, dc_base + UMC_RDATACTL_D1);  in umc_dramcont_init()
109 	writel(0x04060802, dc_base + UMC_WDATACTL_D0);  in umc_dramcont_init()
110 	writel(0x04060802, dc_base + UMC_WDATACTL_D1);  in umc_dramcont_init()
111 	writel(0x04a02000, dc_base + UMC_DATASET);  in umc_dramcont_init()
112 	writel(0x00000000, ca_base + 0x2300);  in umc_dramcont_init()
113 	writel(0x00400020, dc_base + UMC_DCCGCTL);  in umc_dramcont_init()
114 	writel(0x0000000f, dc_base + 0x7000);  in umc_dramcont_init()
115 	writel(0x0000000f, dc_base + 0x8000);  in umc_dramcont_init()
116 	writel(0x000000c3, dc_base + 0x8004);  in umc_dramcont_init()
117 	writel(0x00000071, dc_base + 0x8008);  in umc_dramcont_init()
118 	writel(0x00000004, dc_base + UMC_FLOWCTLG);  in umc_dramcont_init()
119 	writel(0x00000000, dc_base + 0x0060);  in umc_dramcont_init()
120 	writel(0x80000201, ca_base + 0xc20);  in umc_dramcont_init()
121 	writel(0x0801e01e, dc_base + UMC_FLOWCTLA);  in umc_dramcont_init()
122 	writel(0x00200000, dc_base + UMC_FLOWCTLB);  in umc_dramcont_init()
123 	writel(0x00004444, dc_base + UMC_FLOWCTLC);  in umc_dramcont_init()
124 	writel(0x200a0a00, dc_base + UMC_SPCSETB);  in umc_dramcont_init()
125 	writel(0x00010000, dc_base + UMC_SPCSETD);  in umc_dramcont_init()
126 	writel(0x80000020, dc_base + UMC_DFICUPDCTLA);  in umc_dramcont_init()
128 	return 0;  in umc_dramcont_init()
135 	void __iomem *phy_base = dc_base + 0x00001000;  in umc_ch_init()
143 	for (phy = 0; phy < nr_phy; phy++) {  in umc_ch_init()
144 		writel(0x00000100 | ((1 << (phy + 1)) - 1),  in umc_ch_init()
156 		phy_base += 0x00001000;  in umc_ch_init()
165 	void __iomem *umc_base = (void __iomem *)0x5b800000;  in uniphier_pro4_umc_init()
166 	void __iomem *ca_base = umc_base + 0x00001000;  in uniphier_pro4_umc_init()
167 	void __iomem *dc_base = umc_base + 0x00400000;  in uniphier_pro4_umc_init()
171 	for (ch = 0; ch < DRAM_CH_NR; ch++) {  in uniphier_pro4_umc_init()
181 		ca_base += 0x00001000;  in uniphier_pro4_umc_init()
182 		dc_base += 0x00200000;  in uniphier_pro4_umc_init()
187 	return 0;  in uniphier_pro4_umc_init()