Lines Matching +full:0 +full:x07ffffff

24 	/* set 0 to SNRT(UPLLCTRL.bit28) and K_LD(UPLLCTRL.bit[27]) */  in upll_init()
26 tmp &= ~0x18000000; in upll_init()
33 tmp &= ~0x07ffffff; in upll_init()
34 tmp |= 0x0228f5c0; in upll_init()
37 tmp &= ~0x07ffffff; in upll_init()
38 tmp |= 0x02328000; in upll_init()
45 tmp |= 0x08000000; in upll_init()
52 tmp |= 0x10000000; in upll_init()
65 tmp |= 0x00000001; in vpll_init()
68 tmp |= 0x00000001; in vpll_init()
71 /* Set 0 to VPLA_K_LD and VPLB_K_LD */ in vpll_init()
73 tmp &= ~0x10000000; in vpll_init()
76 tmp &= ~0x10000000; in vpll_init()
79 /* Set 0 to VPLA_SNRST and VPLB_SNRST */ in vpll_init()
81 tmp &= ~0x10000000; in vpll_init()
84 tmp &= ~0x10000000; in vpll_init()
87 /* Set 0x20 to VPLA_SNRST and VPLB_SNRST */ in vpll_init()
89 tmp &= ~0x0000007f; in vpll_init()
90 tmp |= 0x00000020; in vpll_init()
93 tmp &= ~0x0000007f; in vpll_init()
94 tmp |= 0x00000020; in vpll_init()
101 tmp &= ~0x000fffff; in vpll_init()
102 tmp |= 0x00066664; in vpll_init()
105 tmp &= ~0x000fffff; in vpll_init()
106 tmp |= 0x00066664; in vpll_init()
111 tmp &= ~0x000fffff; in vpll_init()
112 tmp |= 0x000f5800; in vpll_init()
115 tmp &= ~0x000fffff; in vpll_init()
116 tmp |= 0x000f5800; in vpll_init()
122 tmp |= 0x10000000; in vpll_init()
125 tmp |= 0x10000000; in vpll_init()
131 /* Set 0 to VPLA_SNRST and VPLB_SNRST */ in vpll_init()
133 tmp |= 0x10000000; in vpll_init()
136 tmp |= 0x10000000; in vpll_init()
139 /* set 0 to VPLA27WP and VPLA27WP */ in vpll_init()
141 tmp &= ~0x00000001; in vpll_init()
144 tmp |= ~0x00000001; in vpll_init()