Lines Matching +full:0 +full:x503c0100
18 #define UNIPHIER_SSCC 0x500c0000 /* Control Register */
19 #define UNIPHIER_SSCC_BST (0x1 << 20) /* UCWG burst read */
20 #define UNIPHIER_SSCC_ACT (0x1 << 19) /* Inst-Data separate */
21 #define UNIPHIER_SSCC_WTG (0x1 << 18) /* WT gathering on */
22 #define UNIPHIER_SSCC_PRD (0x1 << 17) /* enable pre-fetch */
23 #define UNIPHIER_SSCC_ON (0x1 << 0) /* enable cache */
24 #define UNIPHIER_SSCLPDAWCR 0x500c0030 /* Unified/Data Active Way Control */
25 #define UNIPHIER_SSCLPIAWCR 0x500c0034 /* Instruction Active Way Control */
28 #define UNIPHIER_SSCID 0x503c0100 /* ID Register */
31 #define UNIPHIER_SSCOPE 0x506c0244 /* Cache Operation Primitive Entry */
32 #define UNIPHIER_SSCOPE_CM_INV 0x0 /* invalidate */
33 #define UNIPHIER_SSCOPE_CM_CLEAN 0x1 /* clean */
34 #define UNIPHIER_SSCOPE_CM_FLUSH 0x2 /* flush */
35 #define UNIPHIER_SSCOPE_CM_SYNC 0x8 /* sync (drain bufs) */
36 #define UNIPHIER_SSCOPE_CM_FLUSH_PREFETCH 0x9 /* flush p-fetch buf */
37 #define UNIPHIER_SSCOQM 0x506c0248
38 #define UNIPHIER_SSCOQM_TID_MASK (0x3 << 21)
39 #define UNIPHIER_SSCOQM_TID_LRU_DATA (0x0 << 21)
40 #define UNIPHIER_SSCOQM_TID_LRU_INST (0x1 << 21)
41 #define UNIPHIER_SSCOQM_TID_WAY (0x2 << 21)
42 #define UNIPHIER_SSCOQM_S_MASK (0x3 << 17)
43 #define UNIPHIER_SSCOQM_S_RANGE (0x0 << 17)
44 #define UNIPHIER_SSCOQM_S_ALL (0x1 << 17)
45 #define UNIPHIER_SSCOQM_S_WAY (0x2 << 17)
46 #define UNIPHIER_SSCOQM_CE (0x1 << 15) /* notify completion */
47 #define UNIPHIER_SSCOQM_CW (0x1 << 14)
48 #define UNIPHIER_SSCOQM_CM_MASK (0x7)
49 #define UNIPHIER_SSCOQM_CM_INV 0x0 /* invalidate */
50 #define UNIPHIER_SSCOQM_CM_CLEAN 0x1 /* clean */
51 #define UNIPHIER_SSCOQM_CM_FLUSH 0x2 /* flush */
52 #define UNIPHIER_SSCOQM_CM_PREFETCH 0x3 /* prefetch to cache */
53 #define UNIPHIER_SSCOQM_CM_PREFETCH_BUF 0x4 /* prefetch to pf-buf */
54 #define UNIPHIER_SSCOQM_CM_TOUCH 0x5 /* touch */
55 #define UNIPHIER_SSCOQM_CM_TOUCH_ZERO 0x6 /* touch to zero */
56 #define UNIPHIER_SSCOQM_CM_TOUCH_DIRTY 0x7 /* touch with dirty */
57 #define UNIPHIER_SSCOQAD 0x506c024c /* Cache Operation Queue Address */
58 #define UNIPHIER_SSCOQSZ 0x506c0250 /* Cache Operation Queue Size */
59 #define UNIPHIER_SSCOQMASK 0x506c0254 /* Cache Operation Queue Address Mask */
60 #define UNIPHIER_SSCOQWN 0x506c0258 /* Cache Operation Queue Way Number */
61 #define UNIPHIER_SSCOPPQSEF 0x506c025c /* Cache Operation Queue Set Complete */
62 #define UNIPHIER_SSCOPPQSEF_FE (0x1 << 1)
63 #define UNIPHIER_SSCOPPQSEF_OE (0x1 << 0)
64 #define UNIPHIER_SSCOLPQS 0x506c0260 /* Cache Operation Queue Status */
65 #define UNIPHIER_SSCOLPQS_EF (0x1 << 2)
66 #define UNIPHIER_SSCOLPQS_EST (0x1 << 1)
67 #define UNIPHIER_SSCOLPQS_QST (0x1 << 0)
70 #define UNIPHIER_SSC_RANGE_OP_MAX_SIZE (0x00400000 - (UNIPHIER_SSC_LINE_SIZE))
124 uniphier_cache_maint_common(0, 0, 0, UNIPHIER_SSCOQM_S_ALL | operation); in uniphier_cache_maint_all()
190 uniphier_cache_maint_common(0, 0, ways, in uniphier_cache_inv_way()
197 void __iomem *base = (void __iomem *)UNIPHIER_SSCC + 0xc00; in uniphier_cache_set_active_ways()
200 case 0x12: /* LD4 */ in uniphier_cache_set_active_ways()
201 case 0x16: /* sld8 */ in uniphier_cache_set_active_ways()
202 base = (void __iomem *)UNIPHIER_SSCC + 0x840; in uniphier_cache_set_active_ways()
205 base = (void __iomem *)UNIPHIER_SSCC + 0xc00; in uniphier_cache_set_active_ways()
231 uniphier_cache_endisable(0); in uniphier_cache_disable()
247 uniphier_cache_maint_range(start, end, 0, UNIPHIER_SSCOQM_CM_FLUSH); in v7_outer_cache_flush_range()
254 uniphier_cache_maint_range(start, UNIPHIER_SSC_LINE_SIZE, 0, in v7_outer_cache_inval_range()
266 uniphier_cache_maint_range(end, UNIPHIER_SSC_LINE_SIZE, 0, in v7_outer_cache_inval_range()
275 uniphier_cache_maint_range(start, end, 0, UNIPHIER_SSCOQM_CM_INV); in v7_outer_cache_inval_range()
280 uniphier_cache_set_active_ways(0, U32_MAX); /* activate all ways */ in v7_outer_cache_enable()