2  * Copyright (c) 2014-2015, NVIDIA CORPORATION.  All rights reserved.
4  * SPDX-License-Identifier: GPL-2.0
7 #define pr_fmt(fmt) "tegra-xusb-padctl: " fmt
14 #include "../xusb-padctl-common.h"
18 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
35 	"xusb",
37 	"pcie-x1",
38 	"pcie-x4",
75 	TEGRA210_LANE("otg-0",     0x004,  0, 0x3, 0, otg),
76 	TEGRA210_LANE("otg-1",     0x004,  2, 0x3, 0, otg),
77 	TEGRA210_LANE("otg-2",     0x004,  4, 0x3, 0, otg),
78 	TEGRA210_LANE("otg-3",     0x004,  6, 0x3, 0, otg),
79 	TEGRA210_LANE("usb2-bias", 0x004, 18, 0x3, 0, otg),
80 	TEGRA210_LANE("hsic-0",    0x004, 14, 0x1, 0, usb),
81 	TEGRA210_LANE("hsic-1",    0x004, 15, 0x1, 0, usb),
82 	TEGRA210_LANE("pcie-0",    0x028, 12, 0x3, 1, pci),
83 	TEGRA210_LANE("pcie-1",    0x028, 14, 0x3, 2, pci),
84 	TEGRA210_LANE("pcie-2",    0x028, 16, 0x3, 3, pci),
85 	TEGRA210_LANE("pcie-3",    0x028, 18, 0x3, 4, pci),
86 	TEGRA210_LANE("pcie-4",    0x028, 20, 0x3, 5, pci),
87 	TEGRA210_LANE("pcie-5",    0x028, 22, 0x3, 6, pci),
88 	TEGRA210_LANE("pcie-6",    0x028, 24, 0x3, 7, pci),
89 	TEGRA210_LANE("sata-0",    0x028, 30, 0x3, 8, pci),
97 static int tegra_xusb_padctl_enable(struct tegra_xusb_padctl *padctl)  in tegra_xusb_padctl_enable()  argument
101 	if (padctl->enable++ > 0)  in tegra_xusb_padctl_enable()
104 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);  in tegra_xusb_padctl_enable()
106 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);  in tegra_xusb_padctl_enable()
110 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);  in tegra_xusb_padctl_enable()
112 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);  in tegra_xusb_padctl_enable()
116 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);  in tegra_xusb_padctl_enable()
118 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);  in tegra_xusb_padctl_enable()
123 static int tegra_xusb_padctl_disable(struct tegra_xusb_padctl *padctl)  in tegra_xusb_padctl_disable()  argument
127 	if (padctl->enable == 0) {  in tegra_xusb_padctl_disable()
132 	if (--padctl->enable > 0)  in tegra_xusb_padctl_disable()
135 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);  in tegra_xusb_padctl_disable()
137 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);  in tegra_xusb_padctl_disable()
141 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);  in tegra_xusb_padctl_disable()
143 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);  in tegra_xusb_padctl_disable()
147 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);  in tegra_xusb_padctl_disable()
149 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);  in tegra_xusb_padctl_disable()
158 	err = tegra_xusb_padctl_enable(phy->padctl);  in phy_prepare()
171 	return tegra_xusb_padctl_disable(phy->padctl);  in phy_unprepare()
218 	struct tegra_xusb_padctl *padctl = phy->padctl;  in pcie_phy_enable()  local
224 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);  in pcie_phy_enable()
227 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);  in pcie_phy_enable()
229 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL5);  in pcie_phy_enable()
232 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL5);  in pcie_phy_enable()
234 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);  in pcie_phy_enable()
236 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);  in pcie_phy_enable()
238 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);  in pcie_phy_enable()
240 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);  in pcie_phy_enable()
242 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);  in pcie_phy_enable()
244 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);  in pcie_phy_enable()
246 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL4);  in pcie_phy_enable()
251 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL4);  in pcie_phy_enable()
253 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);  in pcie_phy_enable()
257 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);  in pcie_phy_enable()
259 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);  in pcie_phy_enable()
261 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);  in pcie_phy_enable()
263 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);  in pcie_phy_enable()
265 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);  in pcie_phy_enable()
269 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL4);  in pcie_phy_enable()
271 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL4);  in pcie_phy_enable()
273 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);  in pcie_phy_enable()
275 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);  in pcie_phy_enable()
282 		value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);  in pcie_phy_enable()
288 		return -ETIMEDOUT;  in pcie_phy_enable()
292 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);  in pcie_phy_enable()
294 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);  in pcie_phy_enable()
301 		value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);  in pcie_phy_enable()
307 		return -ETIMEDOUT;  in pcie_phy_enable()
311 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);  in pcie_phy_enable()
313 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);  in pcie_phy_enable()
319 		value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);  in pcie_phy_enable()
325 		return -ETIMEDOUT;  in pcie_phy_enable()
329 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);  in pcie_phy_enable()
332 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);  in pcie_phy_enable()
338 		value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);  in pcie_phy_enable()
344 		return -ETIMEDOUT;  in pcie_phy_enable()
348 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);  in pcie_phy_enable()
350 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);  in pcie_phy_enable()
356 		value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);  in pcie_phy_enable()
362 		return -ETIMEDOUT;  in pcie_phy_enable()
366 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);  in pcie_phy_enable()
368 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);  in pcie_phy_enable()
377 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);  in pcie_phy_enable()
379 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);  in pcie_phy_enable()
381 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);  in pcie_phy_enable()
383 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);  in pcie_phy_enable()
385 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);  in pcie_phy_enable()
387 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);  in pcie_phy_enable()
415 		.padctl = &padctl,
437 						"nvidia,tegra210-xusb-padctl");  in tegra_xusb_padctl_init()
448 		count = fdtdec_find_aliases_for_id(gd->fdt_blob, "padctl",  in tegra_xusb_padctl_init()