75 	TEGRA210_LANE("otg-0",     0x004,  0, 0x3, 0, otg),
76 	TEGRA210_LANE("otg-1",     0x004,  2, 0x3, 0, otg),
77 	TEGRA210_LANE("otg-2",     0x004,  4, 0x3, 0, otg),
78 	TEGRA210_LANE("otg-3",     0x004,  6, 0x3, 0, otg),
79 	TEGRA210_LANE("usb2-bias", 0x004, 18, 0x3, 0, otg),
80 	TEGRA210_LANE("hsic-0",    0x004, 14, 0x1, 0, usb),
81 	TEGRA210_LANE("hsic-1",    0x004, 15, 0x1, 0, usb),
82 	TEGRA210_LANE("pcie-0",    0x028, 12, 0x3, 1, pci),
83 	TEGRA210_LANE("pcie-1",    0x028, 14, 0x3, 2, pci),
84 	TEGRA210_LANE("pcie-2",    0x028, 16, 0x3, 3, pci),
85 	TEGRA210_LANE("pcie-3",    0x028, 18, 0x3, 4, pci),
86 	TEGRA210_LANE("pcie-4",    0x028, 20, 0x3, 5, pci),
87 	TEGRA210_LANE("pcie-5",    0x028, 22, 0x3, 6, pci),
88 	TEGRA210_LANE("pcie-6",    0x028, 24, 0x3, 7, pci),
89 	TEGRA210_LANE("sata-0",    0x028, 30, 0x3, 8, pci),
92 #define XUSB_PADCTL_ELPG_PROGRAM 0x024
101 	if (padctl->enable++ > 0)  in tegra_xusb_padctl_enable()
102 		return 0;  in tegra_xusb_padctl_enable()
120 	return 0;  in tegra_xusb_padctl_enable()
127 	if (padctl->enable == 0) {  in tegra_xusb_padctl_disable()
129 		return 0;  in tegra_xusb_padctl_disable()
132 	if (--padctl->enable > 0)  in tegra_xusb_padctl_disable()
133 		return 0;  in tegra_xusb_padctl_disable()
151 	return 0;  in tegra_xusb_padctl_disable()
159 	if (err < 0)  in phy_prepare()
162 	reset_set_enable(PERIPH_ID_PEX_USB_UPHY, 0);  in phy_prepare()
164 	return 0;  in phy_prepare()
174 #define XUSB_PADCTL_UPHY_PLL_P0_CTL1 0x360
175 #define  XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_NDIV_MASK (0xff << 20)
176 #define  XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_NDIV(x) (((x) & 0xff) << 20)
177 #define  XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_MDIV_MASK (0x3 << 16)
181 #define  XUSB_PADCTL_UPHY_PLL_P0_CTL1_SLEEP_MASK (0x3 << 1)
182 #define  XUSB_PADCTL_UPHY_PLL_P0_CTL1_SLEEP(x) (((x) & 0x3) << 1)
183 #define  XUSB_PADCTL_UPHY_PLL_P0_CTL1_IDDQ (1 << 0)
185 #define XUSB_PADCTL_UPHY_PLL_P0_CTL2 0x364
186 #define  XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_CTRL_MASK (0xffffff << 4)
187 #define  XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_CTRL(x) (((x) & 0xffffff) << 4)
190 #define  XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_EN (1 << 0)
192 #define XUSB_PADCTL_UPHY_PLL_P0_CTL4 0x36c
194 #define  XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_SEL_MASK (0x3 << 12)
195 #define  XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_SEL(x) (((x) & 0x3) << 12)
197 #define  XUSB_PADCTL_UPHY_PLL_P0_CTL4_REFCLK_SEL_MASK (0xf << 4)
199 #define XUSB_PADCTL_UPHY_PLL_P0_CTL5 0x370
200 #define  XUSB_PADCTL_UPHY_PLL_P0_CTL5_DCO_CTRL_MASK (0xff << 16)
201 #define  XUSB_PADCTL_UPHY_PLL_P0_CTL5_DCO_CTRL(x) (((x) & 0xff) << 16)
203 #define XUSB_PADCTL_UPHY_PLL_P0_CTL8 0x37c
209 #define CLK_RST_XUSBIO_PLL_CFG0 0x51c
214 #define  CLK_RST_XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL (1 << 0)
226 	value |= XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_CTRL(0x136);  in pcie_phy_enable()
231 	value |= XUSB_PADCTL_UPHY_PLL_P0_CTL5_DCO_CTRL(0x2a);  in pcie_phy_enable()
279 	start = get_timer(0);  in pcie_phy_enable()
298 	start = get_timer(0);  in pcie_phy_enable()
302 		if ((value & XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_DONE) == 0)  in pcie_phy_enable()
316 	start = get_timer(0);  in pcie_phy_enable()
335 	start = get_timer(0);  in pcie_phy_enable()
353 	start = get_timer(0);  in pcie_phy_enable()
357 		if ((value & XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_DONE) == 0)  in pcie_phy_enable()
396 	return 0;  in pcie_phy_enable()
401 	return 0;  in pcie_phy_disable()
431 	int count = 0;  in tegra_xusb_padctl_init()
441 			nodes[0] = np_to_ofnode(np);  in tegra_xusb_padctl_init()
451 		for (i = 0; i < count; i++)  in tegra_xusb_padctl_init()