676 	struct clk_rst_ctlr *clkrst =  in clock_get_osc_freq()  local
680 	reg = readl(&clkrst->crc_osc_ctrl);  in clock_get_osc_freq()
702 	struct clk_rst_ctlr *clkrst =  in get_periph_source_reg()  local
708 		return &clkrst->crc_clk_src[PERIPH_ID_CSI+1];  in get_periph_source_reg()
716 		return &clkrst->crc_clk_src[internal_id];  in get_periph_source_reg()
721 		return &clkrst->crc_clk_src_vw[internal_id];  in get_periph_source_reg()
727 		return &clkrst->crc_clk_src_x[internal_id];  in get_periph_source_reg()
732 	return &clkrst->crc_clk_src_y[internal_id];  in get_periph_source_reg()
813 	struct clk_rst_ctlr *clkrst =  in clock_set_enable()  local
821 		clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)];  in clock_set_enable()
823 		clk = &clkrst->crc_clk_out_enb_vw[PERIPH_REG(periph_id)];  in clock_set_enable()
825 		clk = &clkrst->crc_clk_out_enb_x;  in clock_set_enable()
827 		clk = &clkrst->crc_clk_out_enb_y;  in clock_set_enable()
839 	struct clk_rst_ctlr *clkrst =  in reset_set_enable()  local
847 		reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)];  in reset_set_enable()
849 		reset = &clkrst->crc_rst_dev_vw[PERIPH_REG(periph_id)];  in reset_set_enable()
851 		reset = &clkrst->crc_rst_devices_x;  in reset_set_enable()
853 		reset = &clkrst->crc_rst_devices_y;  in reset_set_enable()
937 	struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;  in tegra210_setup_pllp()  local
945 	writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]);  in tegra210_setup_pllp()
949 	writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]);  in tegra210_setup_pllp()
954 	writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]);  in tegra210_setup_pllp()
960 	writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]);  in tegra210_setup_pllp()
972 	struct clk_rst_ctlr *clkrst =  in clock_early_init()  local
1016 	clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc,  in clock_early_init()
1024 	clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_out[1],  in clock_early_init()
1030 	writel(data, &clkrst->crc_pll[CLOCK_ID_DISPLAY].pll_misc);  in clock_early_init()
1036 	struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;  in clk_m_get_rate()  local
1039 	value = readl(&clkrst->crc_spare_reg0);  in clk_m_get_rate()