2  * (C) Copyright 2013-2015
5  * SPDX-License-Identifier:     GPL-2.0+
14 #include <asm/arch/sysctr.h>
16 #include <asm/arch-tegra/clk_rst.h>
17 #include <asm/arch-tegra/timer.h>
51 	CLOCK_TYPE_PC2CC3M_T16,	/* PC2CC3M_T, but w/16-bit divisor (I2C) */
60 	CLOCK_TYPE_NONE = -1,   /* invalid clock type */
125 	/* CLOCK_TYPE_PC2CC3M_T, w/16-bit divisor (I2C) */
351  *	SPDIF - which is both 0x08 and 0x0c
354 #define NONE(name) (-1)
598 	/* Y: 192 (192 - 223) */
680 	reg = readl(&clkrst->crc_osc_ctrl);  in clock_get_osc_freq()
708 		return &clkrst->crc_clk_src[PERIPH_ID_CSI+1];  in get_periph_source_reg()
712 	assert(internal_id != -1);  in get_periph_source_reg()
716 		return &clkrst->crc_clk_src[internal_id];  in get_periph_source_reg()
720 		internal_id -= PERIPHC_VW_FIRST;  in get_periph_source_reg()
721 		return &clkrst->crc_clk_src_vw[internal_id];  in get_periph_source_reg()
726 		internal_id -= PERIPHC_X_FIRST;  in get_periph_source_reg()
727 		return &clkrst->crc_clk_src_x[internal_id];  in get_periph_source_reg()
731 	internal_id -= PERIPHC_Y_FIRST;  in get_periph_source_reg()
732 	return &clkrst->crc_clk_src_y[internal_id];  in get_periph_source_reg()
741 		return -1;  in get_periph_clock_info()
745 		return -1;  in get_periph_clock_info()
749 		return -1;  in get_periph_clock_info()
790  * @return mux value (0-4, or -1 if not found)
808 	return -1;  in get_periph_clock_source()
821 		clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)];  in clock_set_enable()
823 		clk = &clkrst->crc_clk_out_enb_vw[PERIPH_REG(periph_id)];  in clock_set_enable()
825 		clk = &clkrst->crc_clk_out_enb_x;  in clock_set_enable()
827 		clk = &clkrst->crc_clk_out_enb_y;  in clock_set_enable()
847 		reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)];  in reset_set_enable()
849 		reset = &clkrst->crc_rst_dev_vw[PERIPH_REG(periph_id)];  in reset_set_enable()
851 		reset = &clkrst->crc_rst_devices_x;  in reset_set_enable()
853 		reset = &clkrst->crc_rst_devices_y;  in reset_set_enable()
932  * T210 redefines PLLP_OUT2 as PLLP_VCO/DIVP, so do different OUT1-4 setup here.
945 	writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]);  in tegra210_setup_pllp()
949 	writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]);  in tegra210_setup_pllp()
954 	writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]);  in tegra210_setup_pllp()
960 	writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]);  in tegra210_setup_pllp()
1016 	clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc,  in clock_early_init()
1024 	clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_out[1],  in clock_early_init()
1029 	data = (1 << PLLD_ENABLE_CLK) | (1 << pllinfo->lock_ena);  in clock_early_init()
1030 	writel(data, &clkrst->crc_pll[CLOCK_ID_DISPLAY].pll_misc);  in clock_early_init()
1039 	value = readl(&clkrst->crc_spare_reg0);  in clk_m_get_rate()
1047 	struct sysctr_ctlr *sysctr = (struct sysctr_ctlr *)NV_PA_TSC_BASE;  in arch_timer_init()  local
1058 	writel(freq, &sysctr->cntfid0);  in arch_timer_init()
1060 	val = readl(&sysctr->cntcr);  in arch_timer_init()
1062 	writel(val, &sysctr->cntcr);  in arch_timer_init()
1087 	 * Recovery Mode or Boot from USB", sub-section "PLLREFE".  in tegra_pllref_enable()
1112 		return -ETIMEDOUT;  in tegra_pllref_enable()
1162 	 * Recovery Mode or Boot from USB", sub-section "PLLEs".  in tegra_plle_enable()
1214 		return -ETIMEDOUT;  in tegra_plle_enable()
1281 	{ -1, },