29 	struct clk_rst_ctlr *clkrst =  in wb_start()  local
56 	reg = readl(&clkrst->crc_rst_dev[TEGRA_DEV_U]);  in wb_start()
58 	writel(reg, &clkrst->crc_rst_dev[TEGRA_DEV_U]);  in wb_start()
62 	osc_ctrl.word = readl(&clkrst->crc_osc_ctrl);  in wb_start()
65 	writel(osc_ctrl.word, &clkrst->crc_osc_ctrl);  in wb_start()
84 	reg = readl(&clkrst->crc_rst_dev[TEGRA_DEV_L]);  in wb_start()
86 	writel(reg, &clkrst->crc_rst_dev[TEGRA_DEV_L]);  in wb_start()
91 	writel(reg, &clkrst->crc_cpu_cmplx_set);  in wb_start()
104 	writel(CCLK_PLLP_BURST_POLICY, &clkrst->crc_cclk_brst_pol);  in wb_start()
109 	writel(reg, &clkrst->crc_clk_cpu_cmplx);  in wb_start()
112 	reg = readl(&clkrst->crc_clk_out_enb[TEGRA_DEV_L]);  in wb_start()
114 	writel(reg, &clkrst->crc_clk_out_enb[TEGRA_DEV_L]);  in wb_start()
128 	reg = readl(&clkrst->crc_rst_dev[TEGRA_DEV_U]);  in wb_start()
130 	writel(reg, &clkrst->crc_rst_dev[TEGRA_DEV_U]);  in wb_start()
188 	writel(pllx_misc.word, &clkrst->crc_pll_simple[SIMPLE_PLLX].pll_misc);  in wb_start()
189 	writel(pllx_base.word, &clkrst->crc_pll_simple[SIMPLE_PLLX].pll_base);  in wb_start()
192 	writel(pllx_base.word, &clkrst->crc_pll_simple[SIMPLE_PLLX].pll_base);  in wb_start()
194 	writel(pllx_base.word, &clkrst->crc_pll_simple[SIMPLE_PLLX].pll_base);  in wb_start()
199 	writel(reg, &clkrst->crc_cpu_cmplx_clr);  in wb_start()
203 	writel(reg, &clkrst->crc_pll[CLOCK_ID_MEMORY].pll_out[0]);  in wb_start()
208 	writel(reg, &clkrst->crc_sclk_brst_pol);  in wb_start()
211 	reg = readl(&clkrst->crc_rst_dev[TEGRA_DEV_L]);  in wb_start()
213 	writel(reg, &clkrst->crc_rst_dev[TEGRA_DEV_L]);  in wb_start()
226 	writel(SWR_TRIG_SYS_RST, &clkrst->crc_rst_dev[TEGRA_DEV_L]);  in wb_start()