13 #include <asm/arch/emc.h>
17  * The EMC registers have shadow registers.  When the EMC clock is updated
21  * and relies on the clock lock on the emc clock to avoid races between
105  * Find EMC tables for the given ram code.
107  * The tegra EMC binding has two options, one using the ram code and one not.
109  * If this is not present, then the EMC tables are directly below 'node',
110  * otherwise we select the correct emc-tables subnode based on the 'ram_code'
114  * @param node		EMC node (nvidia,tegra20-emc compatible string)
147 		if (strcmp("emc-tables", fdt_get_name(blob, offset, NULL)))  in find_emc_tables()
161  * Decode the EMC node of the device tree, returning a pointer to the emc
166  * @param emcp	Returns address of EMC controller registers
167  * @param tablep Returns pointer to table to program into EMC. There are
185 	 * The EMC clock rate is twice the bus rate, and the bus rate is  in decode_emc()
192 		debug("%s: No EMC node found in FDT\n", __func__);  in decode_emc()
197 		debug("%s: No EMC node reg property\n", __func__);  in decode_emc()
201 	/* Work out the parent node which contains our EMC tables */  in decode_emc()
229 	*tablep = fdtdec_locate_array(blob, node, "nvidia,emc-registers",  in decode_emc()
243 	struct emc_ctlr *emc;  in tegra_set_emc()  local
247 	err = decode_emc(blob, rate, &emc, &table);  in tegra_set_emc()
249 		debug("Warning: no valid EMC (%d), memory timings unset\n",  in tegra_set_emc()
254 	debug("%s: Table found, setting EMC values as follows:\n", __func__);  in tegra_set_emc()
257 		u32 addr = (uintptr_t)emc + emc_reg_addr[i];  in tegra_set_emc()
263 	/* trigger emc with new settings */  in tegra_set_emc()
266 	debug("EMC clock set to %lu\n",  in tegra_set_emc()