18 #define XUSB_PADCTL_ELPG_PROGRAM 0x01c
23 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1 0x040
25 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_REFCLK_SEL_MASK (0xf << 12)
28 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL2 0x044
33 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1 0x138
38 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ (1 << 0)
40 #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1 0x148
42 #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ (1 << 0)
95 	TEGRA124_LANE("otg-0",  0x004,  0, 0x3, 0, otg),
96 	TEGRA124_LANE("otg-1",  0x004,  2, 0x3, 0, otg),
97 	TEGRA124_LANE("otg-2",  0x004,  4, 0x3, 0, otg),
98 	TEGRA124_LANE("ulpi-0", 0x004, 12, 0x1, 0, usb),
99 	TEGRA124_LANE("hsic-0", 0x004, 14, 0x1, 0, usb),
100 	TEGRA124_LANE("hsic-1", 0x004, 15, 0x1, 0, usb),
101 	TEGRA124_LANE("pcie-0", 0x134, 16, 0x3, 1, pci),
102 	TEGRA124_LANE("pcie-1", 0x134, 18, 0x3, 2, pci),
103 	TEGRA124_LANE("pcie-2", 0x134, 20, 0x3, 3, pci),
104 	TEGRA124_LANE("pcie-3", 0x134, 22, 0x3, 4, pci),
105 	TEGRA124_LANE("pcie-4", 0x134, 24, 0x3, 5, pci),
106 	TEGRA124_LANE("sata-0", 0x134, 26, 0x3, 6, pci),
113 	if (padctl->enable++ > 0)  in tegra_xusb_padctl_enable()
114 		return 0;  in tegra_xusb_padctl_enable()
132 	return 0;  in tegra_xusb_padctl_enable()
139 	if (padctl->enable == 0) {  in tegra_xusb_padctl_disable()
141 		return 0;  in tegra_xusb_padctl_disable()
144 	if (--padctl->enable > 0)  in tegra_xusb_padctl_disable()
145 		return 0;  in tegra_xusb_padctl_disable()
163 	return 0;  in tegra_xusb_padctl_disable()
197 	start = get_timer(0);  in pcie_phy_enable()
202 			err = 0;  in pcie_phy_enable()
219 	return 0;  in pcie_phy_disable()
247 	start = get_timer(0);  in sata_phy_enable()
252 			err = 0;  in sata_phy_enable()
283 	return 0;  in sata_phy_disable()
325 	int count = 0;  in tegra_xusb_padctl_init()
335 			nodes[0] = np_to_ofnode(np);  in tegra_xusb_padctl_init()
345 		for (i = 0; i < count; i++)  in tegra_xusb_padctl_init()