26 	debug("%s entry\n", __func__);  in enable_cpu_power_rail()
51 	debug("%s entry\n", __func__);  in enable_cpu_clocks()
56 		debug("%s: PLLX base = 0x%08X\n", __func__, reg);  in enable_cpu_clocks()
59 	debug("%s: PLLX locked, delay for stable clocks\n", __func__);  in enable_cpu_clocks()
63 	debug("%s: Setting CCLK_BURST and DIVIDER\n", __func__);  in enable_cpu_clocks()
67 	debug("%s: Enabling clock to all CPUs\n", __func__);  in enable_cpu_clocks()
73 	debug("%s: Enabling main CPU complex clocks\n", __func__);  in enable_cpu_clocks()
79 	debug("%s: Done\n", __func__);  in enable_cpu_clocks()
87 	debug("%s entry\n", __func__);  in remove_cpu_resets()
120 	debug("%s entry\n", __func__);  in tegra124_init_clocks()
140 	debug("Setting up PLLX\n");  in tegra124_init_clocks()
147 	debug("Enabling clocks\n");  in tegra124_init_clocks()
179 	debug("Taking periphs out of reset\n");  in tegra124_init_clocks()
192 	debug("%s exit\n", __func__);  in tegra124_init_clocks()
209 	debug("%s: part ID = %08X\n", __func__, partid);  in power_partition()
213 		debug("power_partition, toggling state\n");  in power_partition()
228 	debug("%s entry: G cluster\n", __func__);  in powerup_cpus()
231 	debug("%s: CRAIL\n", __func__);  in powerup_cpus()
235 	debug("%s: C0NC\n", __func__);  in powerup_cpus()
239 	debug("%s: CE0\n", __func__);  in powerup_cpus()
242 	debug("%s: done\n", __func__);  in powerup_cpus()
249 	debug("%s entry, reset_vector = %x\n", __func__, reset_vector);  in start_cpu()
263 	debug("%s exit, should continue @ reset_vector\n", __func__);  in start_cpu()